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74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

NXP Semiconductors. 

NXP Semiconductors

74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

VI

MR input

GND

VI

SHCP input

GND

VOH

Q7S output

VOL

VM

tW

t rec

VM

t PHL

VM

mna561

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and

the master reset to shift clock (SHCP) recovery time

OE input

VI

GND

VCC

output

LOW-to-OFF

OFF-to-LOW

VOL

output

HIGH-to-OFF

OFF-to-HIGH

VOH

GND

VM

tPLZ

tPZL

tPHZ

VX

VY

outputs

enabled

VM

tPZH

outputs

disabled

VM

outputs

enabled

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Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 12. Enable and disable times

Table 8. Measurement points

Supply voltage

Input

VCC

VCC < 2.7 V

VCC ≥ 2.7 V

VM

0.5VCC

1.5 V

Output

VM

0.5VCC

1.5 V

VX

VOL + 0.1VCC

VOL + 0.3 V

VY

VOH − 0.1VCC

VOH − 0.3 V

74LV595_3

Product data sheet

Rev. 03 — 21 April 2009

© NXP B.V. 2009. All rights reserved.

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