Nexperia
74AHC594-Q100; 74AHCT594-Q100
8-bit shift register with output register
$+&4
$+&74
4
4
4
4
4
4
4
*1'
9&&
4
'6
675
67&3
6+&3
6+5
46
DDD
Fig 6. Pin configuration (T)SSOP16
$+&4
$+&74
WHUPLQDO
LQGH[DUHD
4
4
4
4
4
4
*1'
4
'6
675
67&3
6+&3
6+5
DDD
7UDQVSDUHQWWRSYLHZ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 7. Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
Q7S
SHR
SHCP
STCP
STR
DS
Q0
VCC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
parallel data output
ground (0 V)
serial data output
shift register reset input (active LOW)
shift register clock input
storage register clock input
storage register reset input (active LOW)
serial data input
parallel data output
supply voltage
74AHC_AHCT594_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© Nexperia B.V. 2017. All rights reserved
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