74AHC594PW-Q100 데이터 시트보기 (PDF) - NXP Semiconductors.
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74AHC594PW-Q100 Datasheet PDF : 24 Pages
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74AHC594-Q100;
74AHCT594-Q100
8-bit shift register with output register
Rev. 2 — 4 July 2013
Product data sheet
1. General description
The 74AHC594-Q100; 74AHCT594-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7A.
The 74AHC594-Q100; 74AHCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out
shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and
STCP) and direct overriding clears (SHR and STR) are provided on both the shift and
storage registers. A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register is always one count pulse ahead of the
storage register.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have Schmitt trigger actions
Inputs accept voltages higher than VCC
Wide supply voltage range from 2.0 V to 5.5 V
8-bit serial-in, parallel-out shift register with storage
Independent direct overriding clears on shift and storage registers
Independent clocks for shift and storage registers
Latch-up performance exceeds 100 mA per JESD78 Class II
Input levels:
For 74AHC594-Q100: CMOS level
For 74AHCT594-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Multiple package options
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