ADP3808AJPZ 데이터 시트보기 (PDF) - ON Semiconductor
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ADP3808AJPZ Datasheet PDF : 15 Pages
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ADP3808A
ELECTRICAL CHARACTERISTICS
VCC = 20 V, EN = 5.0 V, REFIN = 3.0 V, TA = 0°C to 100°C; unless otherwise noted. (Note 1)
Parameter
Symbols
Symbol
Min
Typ
Max Unit
Battery Voltage Sensing
Accuracy
ΔVBAT
TA = 25°C, 13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
5°C ≤ TA ≤ 55°C, 13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
−0.4
−0.6
+0.4
%
+0.6
%
Input Resistance
Shutdown Leakage Current
Overvoltage Threshold
Overvoltage Response Time
Battery Voltage Adjust
BATADJ Input Range
REFIN Input Range
3-Cell Voltage Low
3-Cell Voltage High
4-Cell Voltage Low
4-Cell Voltage High
Battery Current Sense Amplifier
Accuracy (Note 2)
RBAT
IBAT(SD)
VBAT(OV)
tBAT(OV)
VBATADJ
VREFIN
VBAT
VBAT
VBAT
VBAT
13 V ≤ VCC ≤ 21 V,
BATADJ = 0 V or BATADJ = REFIN
EN = 0 V
VBAT(OV) to COMP < 1 V
BATADJ = 0 V, CELLSEL = 3.3 V
BATADJ = REFIN, CELLSEL = 3.3 V
BATADJ = 0 V, CELLSEL = 0 V
BATADJ = REFIN, CELLSEL = 0 V
−0.8
+0.8
%
170
0.2
120
135
1
kW
1.0
mA
%
ms
0
REFIN V
2.0
3.5
V
12.0
V
13.5
V
16.0
V
18.0
V
CSADJ = REFIN, 3 V ≤ VCS(CM) ≤ 21 V
−5
CSADJ = REFIN / 5, 3 V ≤ VCS(CM) ≤
−9
21 V
+5
%
+9
%
0°C ≤ TA ≤ 55°C, CSADJ = REFIN / 32,
−33
3 V ≤ VCS(CM) ≤ 12 V
+33
%
0°C ≤ TA ≤ 55°C, CSADJ = REFIN / 32,
−40
12 V < VCS(CM) ≤ 21 V
+40
%
Input Common Mode Range
Input Bias Current, Operating
Input Bias Current, Shutdown
Input Bias Current, CSM
Gain
CSADJ Bias Current
Overcurrent Threshold (Note 2)
Overcurrent Response Time
VCM(CS)
IB(CSP)
IB(CSP,SD)
IB(CSM)
AV(CS)
IB(CSADJ)
VCS(OC)
tDC
EN = 0 V
VOC > 130 mV to COMP < 1 V
0
VCC
V
40
mA
0.1
1
mA
0.1
2
mA
31.25
V/V
1
2
mA
90
100
110
mV
1
ms
DRVL Shutdown Threshold
VCS(DRVLSD)
28
mV
System Current Sense Amplifier
Input Common Mode Range
Input Bias Current, SYSP
VCM(SYS)
IB(SYSP)
SYSP and SYSM to AGND
VSYS(CM) = 19 V
10
22
V
300
400
mA
Input Bias Current, SYSM
IB(SYSM)
VSYS(CM) = 19 V
0.1
1
mA
Voltage Gain
ISYS Output Current
VISYS/(VSYSP − VSYSM)
VISYS = 2.5 V
49.5
50
51.5 V/V
5
mA
LIMIT Threshold
VTH(LIMIT)
SYSP to SYSM, LIMSET = 2.5 V
48
53
58
mV
LIMSET Input Range
VLIMSET
0
3.5
V
LIMIT Output Voltage Low
VOL(LIMIT)
ILIMIT = −100 mA
30
75
mV
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2. Measured between CSP and CSM. (VCSP − VCSM) = 96 mV x CSADJ/REFIN.
3. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
4. The turn−on of DRVL is initiated after DRVH turns off by either SW crossing a ~1.0 V threshold or by examination of the timeout delay.
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