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LFSC3GA15E-5F256C

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

LatticeSC/M Family Data Sheet

Architecture

June 2008

Data Sheet DS1004

Architecture Overview

The LatticeSC architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR). The upper left and

upper right corners of the devices contain SERDES blocks and their associated PCS blocks, as show in Figure 2-1.

Top left and top right corner of the device contain blocks of SERDES. Each block of SERDES contains four chan-

nels (quad). Each channel contains a single serializer and de-serializer, synchronization and word alignment logic.

The SERDES quad connects with the Physical Coding Sub-layer (PCS) blocks that contain logic to simultaneously

perform alignment, coding, de-coding and other functions. The SERDES quad block has separate supply, ground

and reference voltage pins.

The PICs contain logic to facilitate the conditioning of signals to and from the I/O before they leave or enter the

FPGA fabric. The block provides DDR and shift register capabilities that act as a gearbox between high speed I/O

and the FPGA fabric. The blocks also contain programmable Adaptive Input Logic that adjusts the delay applied to

signals as they enter the device to optimize setup and hold times and ensure robust performance.

sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM, ROM or FIFO. These

blocks have dedicated logic to simplify the implementation of FIFOs.

The PFU, PIC and EBR blocks are arranged in a two-dimensional grid with rows and columns as shown in

Figure 2-1. These blocks are connected with many vertical and horizontal routing channel resources. The place

and route software tool automatically allocates these routing resources.

The corners contain the sysCLOCK Analog Phase Locked Loop (PLL) and Delay Locked Loop (DLL) Blocks. The

PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the

clocks. The LatticeSC architecture provides eight analog PLLs per device and 12 DLLs. The DLLs provide a simple

delay capability and can also be used to calibrate other delays within the device.

Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™

port which allows for serial or parallel device configuration. The system bus simplifies the connections of the exter-

nal microprocessor to the device for tasks such as SERDES and PCS configuration or interface to the general

FPGA logic. The LatticeSC devices use 1.2V as their core voltage operation with 1.0V operation also possible.

© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1004 Architecture_01.9

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