LFSC3GA15E-5F256C 데이터 시트보기 (PDF) - Lattice Semiconductor

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LFSC3GA15E-5F256C

LatticeSC/M Family Data Sheet Introduction

Lattice Semiconductor 

Lattice Semiconductor

Architecture

LatticeSC/M Family Data Sheet

• Two outputs per PLL

• Clock divider outputs

• Digital Clock Select (DCS) block outputs

• Three outputs per SERDES quad

Figure 2-5 shows the arrangement of the primary clock sources.

Figure 2-5. Clock Sources

Edge

Clock

PIOs

Primary/

Edge Clock

PIOs

Primary/

Edge Clock

PIOs

Edge Clock

PIOs

Primary/

Edge Clock

PIOs

PLL

PLL

SERDES

DLL

(3 per SERDES Channel)

DLL

DCS

DCS

24

Clock

Dividers

DLL

DLL

DLL

DLL

PLL

DCS

DCS

SERDES

PLL

Clock Dividers (3 per SERDES Channel)

DLL

DLL

4

Primary/

Edge Clock

PIOs

Edge Clock

PIOs

Primary Clock Sources

8

DCS

24

DCS

Clock

Dividers

DLL

DLL

DLL

DLL

Primary/

Edge Clock

PIOs

PLL

Clock Dividers

Clock Dividers

PLL

DCS

DCS

PLL

PLL

Edge

Clock

PIOs

Primary/

Edge Clock

PIOs

Edge

Clock

PIOs

Primary/

Edge Clock

PIOs

Primary Clock Routing

The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary

clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from

local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6

shows this clock routing.

2-7

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