LFSC3GA15E-5F256C 데이터 시트보기 (PDF) - Lattice Semiconductor
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LFSC3GA15E-5F256C Datasheet PDF : 237 Pages
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LatticeSC/M Family Data Sheet
Introduction
January 2008
Data Sheet DS1004
Features
■ High Performance FPGA Fabric
• 15K to 115K four input Look-up Tables (LUT4s)
• 139 to 942 I/Os
• 700MHz global clock; 1GHz edge clocks
■ 4 to 32 High Speed SERDES and flexiPCS™
(per Device)
• Performance ranging from 600Mbps to 3.8Gbps
• Excellent Rx jitter tolerance (0.8UI at
3.125Gbps)
• Low Tx jitter (0.25UI typical at 3.125Gbps)
• Built-in Pre-emphasis and equalization
• Low power (typically 105mW per channel)
• Embedded Physical Coding Sublayer (PCS)
provides pre-engineered implementation for the
following standards:
– GbE, XAUI, PCI Express, SONET, Serial
RapidIO, 1G Fibre Channel, 2G Fibre Channel
■ 2Gbps High Performance PURESPEED™ I/O
• Supports the following performance bandwidths
– Differential I/O up to 2Gbps DDR
(1GHz Clock)
– Single-ended memory interfaces up to
800Mbps
• 144 Tap programmable Input Delay (INDEL)
block on every I/O dynamically aligns data to
clock for robust performance
– 1 to 7.8 Mbits memory
– True Dual Port/Pseudo Dual Port/Single
Port
– Dedicated FIFO logic for all block RAM
– 500MHz performance
• Additional 240K to 1.8Mbits distributed RAM
■ sysCLOCK™ Network
• Eight analog PLLs per device
– Frequency range from 15MHz to 1GHz
– Spread spectrum support
• 12 DLLs per device with direct control of I/O
delay
– Frequency range from 100MHz to 700MHz
• Extensive clocking network
– 700MHz primary and 325 MHz secondary
clocks
– 1GHz I/O-connected edge clocks
• Precision Clock Divider
– Phase matched x2 and x4 division of incom-
ing clocks
• Dynamic Clock Select (DCS)
– Glitch free clock MUX
■ Masked Array for Cost Optimization
(MACO™) Blocks
• On-chip structured ASIC Blocks provide pre-
engineered IP for low power, low cost system
level integration
– Dynamic bit Adaptive Input Logic (AIL) mon- ■ High Performance System Bus
itoring and control circuitry per pin that auto-
• Ties FPGA elements together with a standard
matically ensures proper set-up and hold
bus framework
– Dynamic bus: uses control bus from DLL
– Connects to peripheral user interfaces for
– Static per bit
run-time dynamic configuration
• Electrical standards supported:
– LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL
– SSTL 3/2/18 I, II; HSTL 18/15 I, II
■ System Level Support
• IEEE standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer
– PCI, PCI-X
• IEEE Standard 1532 in-system configuration
– LVDS, Mini-LVDS, Bus-LVDS, MLVDS,
LVPECL, RSDS, Hypertransport
• Programmable On Die Termination (ODT)
• 1.2V and 1.0V operation
• Onboard oscillator for initialization and general
use
– Includes Thevenin Equivalent and low
power VTT termination options
• Embedded PowerPC microprocessor interface
• Low cost wire-bond and high pin count flip-chip
■ Memory Intensive FPGA
• sysMEM™ embedded Block RAM
packaging
• Low cost SPI Flash RAM configuration
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1004 Introduction_01.6
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