WM8772SEDS/RV 데이터 시트보기 (PDF) - Cirrus Logic
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WM8772SEDS/RV Datasheet PDF : 73 Pages
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Production Data
WM8772EDS – 28 LEAD SSOP
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
DOUT propagation delay
from BCLK falling edge
SYMBOL
tDD
Table 4 Digital Audio Data Timing – Slave Mode
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
MPU INTERFACE TIMING
ML/I2S
MC/IWL
tSCY
tSCH
tSCL
tCSL
tCSH
tCSS
tSCS
MD/DM
tDSU
tDHO
LSB
Figure 18 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, DACMCLK and ADCMCLK = 256fs unless otherwise
stated
PARAMETER
SYMBOL
MIN
MC/IWL rising edge to ML/I2S rising edge
tSCS
60
MC/IWL pulse cycle time
tSCY
80
MC/IWL pulse width low
MC/IWL pulse width high
tSCL
30
tSCH
30
MD/DM to MC/IWL set-up time
tDSU
20
MC/IWL to MD/DM hold time
tDHO
20
ML/I2S pulse width low
tCSL
20
ML/I2S pulse width high
tCSH
20
ML/I2S rising to MC/IWL rising
tCSS
20
Table 5 3-Wire SPI Compatible Control Interface Input Timing Information
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
w
PD Rev 4.2 October 2005
19
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