WM8772SEDS/RV 데이터 시트보기 (PDF) - Cirrus Logic
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WM8772SEDS/RV Datasheet PDF : 73 Pages
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Production Data
WM8772EDS – 28 LEAD SSOP
SAMPLING
RATE
(LRC)
128fs
System Clock Frequency (MHz)
192fs
256fs
384fs
512fs
768fs
32kHz
4.096
6.144
8.192
12.288
16.384
24.576
44.1kHz
5.6448
8.467
11.2896 16.9340 22.5792 33.8688
48kHz
6.144
9.216
12.288
18.432
24.576
36.864
96kHz
12.288 18.432
24.576
36.864 Unavailable Unavailable
192kHz
24.576 36.864 Unavailable Unavailable Unavailable Unavailable
Table 6 System Clock Frequencies Versus Sampling Rate
(ADC does not support 128fs and 192fs)
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available.
Note: When in hardware mode the ADC and DAC will only run in slave mode.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be
used to enable and disable the automute function. This pin becomes an output when left floating and
indicates infinite ZERO detect (IZD) has been detected.
DESCRIPTION
0
1
Floating
Normal Operation
Mute DAC channels
Enable IZD, MUTE becomes an output to indicate when IZD occurs.
L=IZD detected, H=IZD not detected.
Table 7 Mute and Automute Control
Figure 19 shows the application and release of MUTE whilst a full amplitude sinusoid is being played
at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to
decay exponentially from the DC level of the last input sample. The output will decay towards VMID
with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024
or more input samples the outputs will be connected directly to VMID if IZD is set. When MUTE is de-
asserted, the output will restart immediately from the current input sample.
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
Time(s)
Figure 19 Application and Release of Soft Mute
w
0.004
0.005
0.006
PD Rev 4.2 October 2005
21
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