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BT8110

High-Capacity ADPCM Processor

Conexant Systems 

Appendix C . E1 Speech Compression

C.1 Introduction

Bt8110/8110B

High-Capacity ADPCM Processor

A 2.048 MHz bit clock is then provided at BITCKO. This bit clock is used as

the clock input to both the transmitter circuit and the slip buffer circuit. This

procedure ensures proper alignment of the Bt8110/8110B bit and system clocks.

Figure C-1. E1 Speech Compression Interface Configuration

32.768 MHz

VCXO

CK160

SYSCKI

SLPSYNCI

XYSNCO

SLPPCMO

E1

Framer

Bt8510

XPCMI

BITCKO

XCKI

SLPCKI

XSYNCI

Microprocessor

÷2 CLOCK

PSIG[7:0]

8 ADPCM_Input

ADPCM_STB

SYNC

SERIAL_IN

SERIAL_OUT

ADPCM

Processor

Bt8110/B

MICREN

RESET

PSIGEN

PCM_STB

+5 V

PSIG[0]

A[13:0]

D[7:0]

EXT

ROM

8

D (ADPCM Output)

100060_023

If the 32.768 MHz signal source is then phase-locked to the received clock (by

phase-locking the slip buffer sync output to the receive sync output) then the

transmit and receive clocks will be synchronized and no frame slips will appear at

the receiver.

The full-rate PCM inputs and outputs to the Bt8110/8110B are serial and are

configured to connect directly to the Bt8510. The SERIAL_IN and

SERIAL_OUT signals of the Bt8110/8110B connect directly to the slip buffer

output and the transmit input of the framer, respectively. The Bt8110/8110B

frame synchronization is determined by the SYNC input, which can be obtained

from the free-running synchronization signal XSYNCO from the Bt8510 (this

signal must also be connected to SLPSYNCI to synchronize the receive slip

buffer).

The ADPCM inputs and outputs are timed by the signal ADPCM_STB. The

input to the Bt8110/8110B is applied to the parallel input PSIG[7:0], with the

most significant bit at PSIG[7]. The output is obtained from the ROM data bus

D[7:0], with the most significant bit at D[7].

The input data must be valid at the positive edge of ADPCM_STB and the

output data is valid at the positive edge. Due to the processing delay of the

Bt8110/8110B, there is a five-channel offset between the timing of the ADPCM

input and output.

The ADPCM output is always 5 bits (for 40 kbit/s coding and for all

embedded codes) or less. The input includes up to 5 ADPCM input bits and 2 bits

to indicate the number of bits in the decoder input when embedded encoding is

used.

C-2

Conexant

100060C

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