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BT8110

High-Capacity ADPCM Processor

Conexant Systems 

C

Appendix C. E1 Speech Compression

C.1 Introduction

This appendix details of operation of the Bt8110/8110B ADPCM Processor with

the Bt8510 E1 Framer/LIU (or Bt8370 T1/E1 Framer/LIU) for application to

speech compression. This mode can be used to provide full-duplex speech

compression to 16, 24, 32, or 40 kbit/s using a number of embedded and

non-embedded codes.

The Bt8110/8110B provides the coding algorithms specified in ITU–T

Recommendation G.726 and ANSI Standard T1.303-1989 at 40, 32, 24, and 16

kbit/s. It also provides the embedded codes in ITU–T Recommendation G.727

and ANSI Standard T1.310-1991. The 32 kbit/s ADPCM algorithm is also used

in the AMIS version 1 digital messaging protocol.

The speech compression application for 30 channels requires a Bt8510 E1

Framer circuit, a Bt8110/8110B (with an associated 128 K ROM for the Bt8110),

and a microprocessor for configuration and control. Up to 14 separate coding

algorithms can be selected by the controller on a channel-by-channel basis. This

application requires approximately 20 square inches and approximately 1.5 Watts

of power from a +5 V supply.

C.1.1 Configuration

Figure C-1 illustrates a configuration of the Bt8110/8110B and the Bt8510. The

Bt8510 transmits and receives a digital line at the 2.048 Mbit/s primary rate. The

slip buffer of the Bt8510 frame-synchronizes the receive signal to the transmit

signal so that the Bt8110/8110B can operate synchronously on both signals.

A single microprocessor can be used to control the Bt8510 and the

Bt8110/8110B. The only control requirement of the microprocessor is to

configure the operating mode and the per-channel control registers that set the

code rate and reset the algorithm on each channel, as desired. The Bt8510 and the

Bt8110/8110B each have a chip select input that can be used to select the desired

device.

The Bt8510 includes an integral digital timing recovery circuit and analog

interface that is compatible with either 75 Ω cable or 120 Ω twisted-pair wire and

meets the requirements of ITU–T Recommendation G.703. The timing recovery

circuit requires a 32.768 MHz clock signal. The Bt8510 provides a 16.384 MHz

output which can be divided by 2 to provide the 8.192 MHz clock required by the

Bt8110/8110B and can also be provided to the system clock input.

100060C

Conexant

C-1

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