BT8110 데이터 시트보기 (PDF) - Conexant Systems
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BT8110 Datasheet PDF : 84 Pages
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Bt8110/8110B
High-Capacity ADPCM Processor
Appendix B . T1 Speech Compression
B.1 Introduction
B.1.3 Microprocessor Interface And Per-Channel Configuration
The microprocessor interface of the Bt8300 provides all control and status
functions for the T1 lines; it can also be used to insert and extract signaling in this
application.
Table B-1 lists the connections for the Bt8110/8110B. Only 7 bits of the
address/data bus are required. The Bt8110/8110B can be operated by either an
8051-type or a 68HC11-type interface. Only the 8051-type connections are given
here, since the Bt8300 requires this interface. The 68HC11 microprocessor can be
used as well; two gates are required to derive the read and write control signals
needed to emulate the 8051. The Bt8360 T1 Framer and the Bt8370 T1/E1
Framer/LIU interface directly with either the 8051-type or the 68HC11-type
microprocessor.
Table B-1. Bt8110/8110B Microprocessor Connection
ADPCM Processor Pin
Function
Intel 8051
MICREN
ALE
WR*
CS
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
Enable
Address Latch Enable
Write Enable
Chip Select
Address/Data
Address/Data
Address/Data
Address/Data
Address/Data
Address/Data
Address/Data
Vcc
ALE
WR*
A-n
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
Table B-2 lists the address map and the bit interpretations of the control fields.
In this application address 0x40 must be set to a value of 0x14 to properly set the
mode of the Bt8110/8110B. A write to any address in the range 0x40–0x3F will
cause the mode of the Bt8110/8110B to be set.
Table B-2 also provides the per-channel control register bit interpretations.
Bits D[3:0] of each encoder and decoder channel control select the particular
ADPCM code to be used; note that hex values of 6 and 7 are invalid for these bit
positions. ROM codes are available from Conexant with the evaluation board. Bit
D[6] enables A-law PCM coding when set. Bit D[5] enables the algorithm
RESET function. This operation sets the internal parameters of the Bt8110/8110B
to fixed values, as specified in ANSI Standard T1.303-1989 and ITU-T G.726.
Bit D[4] enables transparent operation.
For the encoder channels, when the transparent bit is set all 8 PCM bits are
transferred to the output with the same delay as when ADPCM encoding is taking
place. Full 8-bit (64 kbit/s) transparent operation is not a valid option for the T1
speech compression interface configuration using the Bt8110/8110B. 64 kbit/s
transparent operation is valid with the Bt8110/8110BB. For the decoder, the five
ADPCM inputs and two embedded encoding inputs are transferred to the PCM
100060C
Conexant
B-5
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