AS5SS256K36ADQ-8.5/IT 데이터 시트보기 (PDF) - Austin Semiconductor
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AS5SS256K36ADQ-8.5/IT Datasheet PDF : 16 Pages
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Austin Semiconductor, Inc.
SSRAM
AS5SS256K36 &
AS5SS256K36A
TRUTH TABLE
OPERATION
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
ADDRESS
USED
CE\
CE2\
CE2
ZZ
ADSP\ ADSC\
ADV\
WRITE\ OE\ CLK
DQ
None
HXX L
X
L
X
X
X L-H High-Z
None
LXLL
L
X
X
X
X L-H High-Z
None
L HX L
L
X
X
X
X L-H High-Z
None
LXLL
H
L
X
X
X L-H High-Z
None
L HX L
H
L
X
X
X L-H High-Z
None
XXXH
X
X
X
X
X X High-Z
External L L H L
L
X
X
X
L L-H Q
External L L H L
L
X
X
X
H L-H High-Z
External L L H L
H
L
X
L
X L-H D
External L L H L
H
L
X
H
L L-H Q
External L L H L
H
L
X
H
H L-H High-Z
Next
XXXL
H
H
L
H
L L-H Q
Next
XXXL
H
H
L
H
H L-H High-Z
Next
HXX L
X
H
L
H
L L-H Q
Next
HXX L
X
H
L
H
H L-H High-Z
Next
XXXL
H
H
L
L
X L-H D
Next
HXX L
X
H
L
L
X L-H D
Current X X X L
H
H
H
H
L L-H Q
Current X X X L
H
H
H
H
H L-H High-Z
Current H X X L
X
H
H
H
L L-H Q
Current H X X L
X
H
H
H
H L-H High-Z
Current X X X L
H
H
H
L
X L-H D
Current H X X L
X
H
H
L
X L-H D
NOTE:
1. X means “Don’t Care.” \ means active LOW. H Means logic HIGH. L means logic LOW.
2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\, BWc\, or BWd\) and BWE\ are LOW or
GW\ is LOW. WRITE\ = H for all BWx\, BWE\, GW\ HIGH.
3. BWa\ enables WRITEs to DQa pins, DQPa. BWb\ enables WRITEs to DQb pins, DQPb. BWc\ enables WRITEs to DQc
pins, DQPc. BWd\ enables WRITEs to DQd pins, DQPd.
4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
AS5SS256K36 &
AS5SS256K36A
Rev. 3.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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