MX86251 데이터 시트보기 (PDF) - Macronix International

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MX86251

3D graphic chipset

Macronix International 

MX86251

3Dfx Related Interface Pins:

Pin Name Pin No. Type

PRXRST# 168

O

PMCK3DFX 182

O

PFXSWAP 183

I

PMRQ# 192

IO

PFXGNT# 193

IO

PFXSTS 194

IO

POE1#

195

IO

Description

This is the hardware reset signal for 3CFX interface. It is connected directly to

HRESET# input of 3DFX reset will be reflected on this pin. Software reset pin

SRESET# of 3DFX can be tighten to VDD.

This is the PUMA clock for 3DFX interface. GUI sends this signal to the input

clock pin of 3DFX.

This is the SWAP request from 3DFX. GUI is notified by it to swap CRT or VP

double buffers.

It is also used to detect 3DFX's existence during power-on reset. When

receiving low, it means 3DFX is connected. Otherwise, 3DFX is not connected.

This is a multi-function pin.

If VMI is used, it is used as bit 4 of the host data bus, which is bidirectional.

It is an output pin for pixel data 12 (p12) if PIXTEST is on.

Otherwise, it‘s used as an output pin of the PUMA request for 3DFX interface.

GUI uses this signal to request memory accesses through PUMA.

This is a multi-function pin.

If VMI is used, it is bit 5 of the host data bus.

It is an output pin for pixel data 13 (P13) if PIXTEST is on.

Otherwise, it's used as an input pin of the PUMA grant for 3DFX interface. GUI

will drive DRAM interface signals when this signal is active.

This is a multi-function pin.

If VMI is used, it is bit 6 of the host data bus.

It is an output pin for pixel data 14 (P14) if PIXTEST is on.

Otherwise, it's used as an input of the serial status from 3DFX. GUI will

accumulate it to a 16 bit MMIO register.

This is a multi-function pin. If VMI is used, it is bit 7 of the host data bus.

It is an output pin for pixel data 15 (P15) if PIXTEST is on. Otherwise, it's used

as the output pin OE#1, which is the OE# control signal for high bank of DRAM.

P/N:PM0476

REV. 1.2 , FEB 11, 1998

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