MX86251 데이터 시트보기 (PDF) - Macronix International
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MX86251 Datasheet PDF : 32 Pages
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MX86251
DRAM Interface Pins: (Continued)
Pin Name Pin No. Type
MD0
78
I/O
MD1
77
MD2
76
MD3
75
MD4
74
MD5
72
MD6
71
MD7
70
MD8
69
I/O
MD9
68
MD10
67
MD11
66
MD12
64
MD13
63
MD14
62
MD15
61
MD16
60
I/O
MD17
59
MD18
58
MD19
56
MD20
55
MD21
54
MD22
53
MD23
52
MD24
51
I/O
MD25
50
MD26
49
MD27
47
MD28
46
MD29
45
MD30
44
MD31
43
Description
MD[7:0] is the DRAM data bus of memory plane 0 of bank 0 or bank 1.
In BIOS ROM accesses, these are the data inputs[7:0] of external ROM.
They are also served as power-on strapping inputs.
MD[15:8] is the DRAM data bus of memory plane 1 of bank 0 or bank 1.
They are also served as power-on strapping inputs.
MD[23:16] is the DRAM data bus of memory plane 2 of bank 0 or bank 1.
MD[17:16] are also used as power-on strapping inputs.
MD[31:24] is the DRAM data bus of memory plane 3 of bank 0 or bank 1.In
BIOS ROM accesses, MD[31:16] are the address outputs[15:0] for external ROM.
P/N:PM0476
REV. 1.2 , FEB 11, 1998
16
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