MX86251 데이터 시트보기 (PDF) - Macronix International
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MX86251 Datasheet PDF : 32 Pages
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MX86251
Media Port and Feature Connector Related Interface Pins:(Continued)
Pin Name Pin No. Type
TDCLK 152
I
TMCLK 153
I
BLANK# 154
IO
HSYNC# 155
TO
VSYNC# 156
TO
VMIVS
198
IO
SCK
5
IO
P/N:PM0476
Description
It is a dual-function pin.
If external VCG is selected, it is used as DCLK input. Otherwise, it is the video
input pin for video interface.
It is a dual-function pin.
If external VCG is selected, it is used as MCLK input.
Otherwise, it is the CFLEVEL input from CL480 or ODD from SAA7110.
When used as the CFLEVEL from CL480, it indicates that the CL480 Coded
Data FIFO for compressed data is going to be exhausted. GUI will generate the
interrupt signal to inform the software to put more compressed data into CL480.
When used as the ODD signal from SAA7110, it is an odd/even field indication
for interlaced video. When high, it is odd field, otherwise, even field. GUI uses
this to determine the memory location for incoming video data.
This is a multi-function pin.
For 8-bit Feature Connector, when PENFEATL# is high, the internal BLANK#
signal is output to control RAMDAC display. When PENFEATL# is set to 0, it’s
an input from Feature Connector. GUI uses it to control RAMDAC display.
For VMI or SAA7110, it's the HREF input. And for CL480 it's the HSYNC# input.
In either case, it indicates that video data of a scanline is coming in.
It's the HSYNC# output pin, which is the horizontal sync to analog monitor. For
8-bit Feature Connector, it is enabled when PENFEATL# is high or either SAA7110
or CL480 is selected. Otherwise, it is tristated.
I t ’s the HSYNC# output pin, which is the horizontal sync to analog monitor. For
8-bit Feature Connector, it is enabled when PENFEATL# is high or either SAA7110
or CL480 is selected. Otherwise, it is tristated.
If external VCG is selected, this pin is used as one of the MCLK select output,
MCSEL1. MCSEL[2:0] is used to select MCLK frequency from external VCG. If
internal VCG is used, it is an input pin for video interface. It's the VREF for VMI,
VS for SAA7110 and VSYNC# for CL480. Either one indicates that it's the frame
start of input video data.
It's the I2CCLK input/output pin for both SAA7110 interface or DDC2 monitor
control. As an input, the I2C CLK value can be monitored by reading bit 2 of the
memory-mapped register port at offset 31C or bit 2 of the I/O register at 3?5/50.
To generate clock pulses, software can just program either bit 0 of the above
memory-mapped register or bit 5 of the IO register at 3C4/1E. If 0 is programmed,
this pin is pulled low. If 1 is programmed, this pin is tri-stated. With the external
pull-up, it makes I2CCLK go to high state. In this way, clock pulses are
generated.
REV. 1.2 , FEB 11, 1998
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