ADP3156 데이터 시트보기 (PDF) - Analog Devices
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ADP3156 Datasheet PDF : 12 Pages
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During the standby operating state, the 12 V, 5 V and 3.3 V
power supply outputs are disabled, and only a low power 5 V
rail (5VSB) is available. The circuits that must remain active in
standby must be able to run from 5VSB. To accomplish this,
power routing is required to allow switching between normal
and standby supplies. Lack of a 12 V rail in standby makes control
of linear outputs difficult, and with up to 8 A demand from the
1.5 V and 1.8 V rails, an all-linear solution is inefficient.
Figure 13 shows a typical ACP-compliant Pentium III / chipset
power management system using the ADP3155 and ADP3156.
The ADP3155 provides VID switched output and two linear
regulators for standby operation. A charge-pump-doubled 5VSB is
ORed into the supply rail to supply the linear regulators during
standby operation. The VID output collapses when the main
5 V rail collapses, but the N-channel MOSFET linear regu-
lators can continue to supply current from the ~9 V supply.
The ADP3156 provides 1.8 V via its main switching regulator,
and allows efficient linear regulation of 1.5 V rail by using the
1.8 V output as its source.
The design parameters for an ACPI-compliant Pentium III
peripheral system depend on what peripherals are used
(e.g., AGP) and what their specifications are. The following is
an example where the higher of two low system voltages (1.8 V
and 1.5 V) is created directly with the main buck converter, and
also used to supply power for the lower output voltage using the
ADP3156’s linear regulator controller.
Input voltage (power source): VIN = 5 V
Auxiliary voltage: VCC = 12 V
Output voltages and tolerances: V1 = 1.8 V ± 5%, V2 = 1.5 V ±
5%
Maximum output currents: I1MAX = 3 A, I2MAX = 4 A
ADP3156
Slew rate of load current change: di1/dt = di2/dt >10 A/µs
The absence of an inductor on the 1.5 V linear regulated output
allows the output current to respond quickly and the linear
regulator MOSFET’s resistance to be modulated quickly. This,
and some small bypassing capacitors, essentially insulates the
1.5 V output from transient activity on the 1.8 V output. How-
ever, this same fast response characteristic means that any 1.5 V
transient activity will be passed straight through the linear regu-
lator to the 1.8 V output. This means that the 1.8 V output filter
capacitor selection must consider both 1.8 V and 1.5 V load
transients.
In this design example, worst case consideration requires that
the 1.8 V output be designed for transient current loading of
I1MAX + I2MAX = 7 A. Also, because a practical switching regula-
tor design will have a current slew rate of <1 A/µs due to the
inductor, nearly the entire 7 A transient current must be ab-
sorbed by the output capacitors.
CT Selection for Operating Frequency
The ADP3156 uses a constant-off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
high side N-channel MOSFET switch turns on, the voltage
across CT is reset to approximately 3.3 V. During the off-time,
CT is discharged by a constant current of 65 µA. Once CT reaches
2.3 V, a new on-time cycle is initiated. The value of the off-time
is calculated using the continuous-mode operating frequency.
Assuming a nominal operating frequency of fNOM = 200 kHz at
an output voltage of 1.8 V, the corresponding off-time is:
tOFF
=
1
–
VO
VIN
1
fNOM
= 3.2 µs
The timing capacitor can be calculated from the equation:
CT = tOFF × 65 µA = 208 pF
1V
ATX
12V
(OR NLX)
POWER
5V
SUPPLY 3.3V
5V_ALWAYS
ATX_PGOOD
ATX_SHUTDOWN
GND
12V
5V
3.3V
5V_PM
POWER MANAGEMENT
STATE COMMAND
5V_PM
ATX_POWERGOOD ATX_POWER GOOD
ATX_SHUTDOWN
12V
12V
PMSC
5V_PM
ATXPG
POWER
MANAGEMENT VCC
FUNCTIONS
DUAL
OUTPUT
SUPPLY
VCC
ADP3156
MAIN_
CTRLS
LIN_
CTRLS
ADP3155
LIN#2_
CTRLS
LIN#1_
CTRLS
VCC
VID_4:0
MAIN_
CTRLS
TRIPLE
OUTPUT
VID SUPPLY
IN
5V
1.8V FOR
SWITCHER
SB CORE,
OUT
MEM, ETC
CTRLS
5V
IN
SWITCHER
OUT
CPU
CTRLS
VCORE @ VID
1.5V VTT
FOR GTL
1.5V OR 3.3V
VDDQ FOR AGP
TYPEDET# FOR
AGP SELECT
IN
LINEAR
OUT
CTRLS
VDDQ
3.3V_IN
POWER ROUTING
SELECT
1.5V_IN
3.3V
5V_PM
5V_PM
IN
LINEAR#1
OUT
CTRLS
IN
LINEAR#2
OUT
CTRLS
3.3V_PM
FOR POWER
MANAGEMENT
2.5V_PM
FOR CMOS,
CLOCK, MEMORY
Figure 13. ACPI-Compliant Pentium III System Block Diagram
REV. 0
–7–
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