ADP3156 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
ADP3156 Datasheet PDF : 12 Pages
| |||
ADP3156
Feedback Loop Compensation Design for Active Voltage
Positioning
Optimized compensation of the ADP3156 allows the best pos-
sible containment of the peak-to-peak output voltage deviation.
Any practical switching power converter is inherently limited by
the inductor in its output current slew rate to a value much less
than the slew rate of the load. Therefore, any sudden change of
load current will initially flow through the output capacitors,
and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
To correctly implement active voltage positioning, the low fre-
quency output impedance (i.e., the output resistance) of the
converter should be made equal to the maximum ESR of the
output capacitor array. This can be achieved by having a single
pole roll-off of the voltage gain of the gm error amplifier, where
the pole frequency coincides with the ESR zero of the output
capacitor. A gain with single pole roll-off requires that the gm
amplifier output pin be terminated by the parallel combination
of a resistor and capacitor. The required resistor value can be
calculated from the equation:
where:
RC
=
275
275
kΩ
kΩ
×
–
RtTOTAL
RtTOTAL
RtTOTAL
=
16.4
kΩ × RCS × IOMAX
VHI –VLO
where the quantities 16.4 kΩ and 275 kΩ are characteristics of
the ADP3156, the value of the current sense resistor, RCS, has
already been determined as above, and where VHI and VLO are
the respective upper and lower limits allowed for regulation.
Although a single termination resistor equal to RC would yield
the proper voltage positioning gain, the dc biasing of that resis-
tor would determine how the regulation band is centered (i.e.,
note that sometimes the specified regulation band is asymmetri-
cal with respect to the nominal VID voltage.) With the ADP3156,
the offset is already considered as part of the design procedure—
no special provision is required. To accomplish the dc biasing, it
is simplest to use two resistors to terminate the gm output, with
the lower resistor tied to ground and the upper resistor to the
12 V supply of the IC. The values of these resistors can be cal-
culated using:
and:
RUPPER
=
RC
×VDIV
VOS
RLOWER
=
RC
×
VOS
VDIV – VOS
where VDIV is the resistor divider supply voltage (e.g., the rec-
ommended 12 V), and VOS is the offset voltage required on the
amplifier to produce the desired offset at the output. VOS is
calculated using Equation 2, where VOUT(OS) is the offset from
the nominal VID-programmed value to the center of the speci-
fied regulation window for the output voltage. (Note this may be
either positive or negative.) For clarification, that offset is given
by:
VOUT(OS)
=
1
2 (VHI
+VLO
)
–VID
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
CCOMP
=
CO × ESR
RtTOTAL
Trade-Offs Between DC Load Regulation and AC Load
Regulation
Casual observation of the circuit operation—e.g., with a volt-
meter—would make it appear that the dc load regulation ap-
pears to be rather poor compared to a conventional regulator.
This would be especially noticeable under very light or very
heavy loads where the voltage is “positioned” near one of the
extremes of the regulation window rather than near the nominal
center value. It must be noted and understood that this low gain
characteristic (i.e., loose dc load regulation) is inherently re-
quired to allow improved transient containment (i.e., to achieve
tighter ac load regulation). That is, the dc load regulation is
intentionally sacrificed (but kept within specification) in order
to minimize the number of capacitors required to contain the
load transients produced by the CPU.
Linear Regulator
The ADP3156 linear regulator provides a low cost, convenient
and versatile solution for generating a lower supply rail in addi-
tion to the main output. The maximum output load current is
determined by the size and thermal impedance of the external
N-channel power MOSFET that is controlled by the ADP3156.
The output voltage, VO2 in Figure 14, is sensed at the FB pin of
the ADP3156 and compared to an internal 1.2 V reference in a
negative feedback loop which keeps the output voltage in regula-
tion. If the load is being reduced or increased, the FET drive
will also be reduced or increased by the ADP3156 to provide a
well regulated ± 1% accurate output voltage. The output voltage
is programmed by adjusting the value of the external resistor
RPROG, shown in Figure 14.
VO2 = +1.5V
IO2 = 4.0A
VIN = +1.8V
IRL3103
ADP3156
VLDO
FB
1000F/10V
RPROG
5k⍀
20k ⍀
Figure 14. Linear Regulator Configuration
VOS
=
RC
RtTOTAL
×
0.8 V
+ VOUT(OS)1R.3tT6OTkAΩL
– 1.7 V
RtTOTAL
275 kΩ
+6
RCSIOMAX
(2)
–10–
REV. 0
Share Link: 