ADP3156 데이터 시트보기 (PDF) - Analog Devices
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ADP3156 Datasheet PDF : 12 Pages
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ADP3156
Efficiency of the Linear Regulator
The efficiency and corresponding power dissipation of the linear
regulator are not determined by the ADP3156. Rather, these are
a function of input and output voltage and load current. Effi-
ciency is approximated by the formula:
η = 100% × (VOUT Ϭ VIN)
The corresponding power dissipation in the MOSFET, together
with any resistance added in series from input to output is given
by:
× PLDO = (VIN(LDO) – VOUT(LDO)) IOUT(LDO)
Minimum power dissipation and maximum efficiency are ac-
complished by choosing the lowest available input voltage that
exceeds the desired output voltage. However, if the chosen
input source is itself generated by a linear regulator, its power
dissipation will be increased in proportion to the additional
current it must now provide. For most PC systems, the lowest
available input source for the linear regulators, which is not
itself generated by a linear regulator, is 3.3 V from the main
power supply. However, in this case, the main output of the
ADP3156 creates a lower voltage that may be used as the source
supply for the linear regulator. Assuming that a 1.8 V main
output is used to provide power for a 1.5 V linear regulator
output, the efficiency will nominally be 1.5 V ÷ 1.8 V = 83%.
If the 1.5 V output must supply a 4 A maximum load (a total of
6 W), the steady state dissipation in the MOSFET may be as
high as:
PLDO(MAX) = (VIN – VOUT) × IOUT(MAX) = (1.8 V – 1.5 V) × 4 A
= 1.2 W
The minimum acceptable on resistance of the MOSFET that
would deliver the 4 A load with only a 0.3 V difference between
input and output is:
RDS(ON, MAX) = (VOUT – VIN) ÷ IOUT(MAX) = (1.8 V – 1.5 V) ÷ 4 A
= 75 mΩ
There are many MOSFETs to choose from that can support the
maximum power dissipation without need for a heat sink and
without exceeding the calculated maximum on-resistance. For
simplicity it may be desirable to use the same MOSFET as is
used for the main power converter.
The output voltage may be programmed by the RPROG resistor
as follows:
RPROG
=
VO2
1.2 V
– 1
×
20
kΩ
=
1.5
1.2
−
1
×
20
kΩ
=
5
kΩ
The output filter capacitor maximum allowed ESR is:
ESR~VTR2/IOMAX = 0.036/0.5 = 0.072 Ω
where VTR2 is the maximum allowed transient deviation on the
output. This requirement is met using a 1000 µF/10 V LXV
series capacitor from United Chemicon. For applications requir-
ing higher output current, a heat sink and/or a larger MOSFET
should be used to reduce the MOSFET’s junction-to-ambient
thermal impedance.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system:
General Recommendations
1. For best results, a four-layer (minimum) PCB is recom-
mended. This should allow the needed versatility for control
circuitry interconnections with optimal placement, a signal
ground plane, power planes for both power ground and the
input power (e.g., 5 V), and wide interconnection traces in
the rest of the power delivery current paths. Each square
unit of 1 ounce copper trace has a resistance of ~0.53 mΩ at
room temperature.
2. Whenever high currents must be routed between PCB layers
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating is
not exceeded.
3. The power and ground planes should overlap each other as
little as possible. It is generally the easiest (although not
necessary) to have the power and signal ground planes on
the same PCB layer. The planes should be connected near-
est to the first input capacitor where the input ground cur-
rent flows from the converter back to the power source (e.g.,
5 V).
4. If critical signal lines (including the voltage and current
sense lines of the ADP3156) must cross through power
circuitry, it is best if a signal ground plane can be interposed
between those signal lines and the traces of the power cir-
cuitry. This serves as a shield to minimize noise injection
into the signals at the expense of making signal ground a bit
noisier.
5. The PGND pin of the ADP3156 should connect first to a
ceramic bypass capacitor (on the VCC pin) and then into the
power ground plane using the shortest possible trace. How-
ever, the power ground plane should not extend under other
signal components, including the ADP3156 itself. If neces-
sary, follow the preceding guideline to use the signal plane
as a shield between the power ground plane and the signal
circuitry.
6. The AGND pin of the ADP3156 should connect first to the
timing capacitor (on the CT pin), and then into the signal
ground plane. In cases where no signal ground plane can be
used, short interconnections to other signal ground circuitry
in the power converter should be used—the compensation
capacitor being the next most critical.
7. The output capacitors of the power converter should be
connected to the signal ground plan even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections (e.g.,
the signal circuitry of the power converter) in the signal ground
plane in between the input and output capacitors. It is also
advised to keep the planar interconnection path short (i.e.,
have input and output capacitors close together).
8. The output capacitors should also be connected as closely as
possible to the load (or connector) which receives the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors also should be distributed, and generally in pro-
portion to where the load tends to be more dynamic.
REV. 0
–11–
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