AD7866(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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AD7866
(Rev.:Rev0)

Dual 1 MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface

Analog Devices 

AD7866

Pin No. Mnemonic

11

RANGE

12

AVDD

13

DVDD

14

DGND

15, 16

DOUTA, DOUTB

17

VDRIVE

18

SCLK

19

CS

20

A0

PIN FUNCTION DESCRIPTIONS (continued)

Function

Analog Input Range and Output Coding Selection Pin. Logic Input. The polarity on this pin will

determine what input range the analog input channels on the AD7866 will have, and it will also

select what type of output coding the ADC will use for the conversion result. On the falling edge of

CS, the polarity of this pin is checked to determine the analog input range of the next conversion. If

this pin is tied to a logic low, the analog input range is 0 V to VREF and the output coding from the

part will be straight binary (for the next conversion). If this pin is tied to a logic high when CS goes

low, the analog input range is 2 × VREF and the output coding for the part will be two’s complement.

However, if after the falling edge of CS the logic level of the RANGE pin has changed upon the eighth

SCLK falling edge, the output coding will change to the other option without any change in the

analog input range. (See Analog Input and ADC Transfer Function sections.)

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on

the AD7866. The AVDD and DVDD voltages should ideally be at the same potential and must not

be more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND.

Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the

AD7866. The DVDD and AVDD voltages should ideally be at the same potential and must not be

more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND.

Digital Ground. This is the ground reference point for all digital circuitry on the AD7866. The

DGND and AGND voltages should ideally be at the same potential and must not be more than

0.3 V apart even on a transient basis.

Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are

clocked out on the falling edge of the SCLK input. The data appears on both pins simultaneously

from the simultaneous conversions of both ADCs. The data stream consists of one leading zero

followed by three STATUS bits, followed by the 12 bits of conversion data. The data is provided

MSB first. If CS is held low for a further 16 SCLK cycles after the conversion data has been output

on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows

data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA

or DOUTB alone using only one serial port. See Serial Interface section.

Logic Power Supply Input. The voltage supplied at this pin determines what voltage the interface

will operate at. This pin should be decoupled to DGND.

Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the

AD7866. This clock is also used as the clock source for the conversion process.

Chip Select. Active low logic input. This input provides the dual function of initiating conversions

on the AD7866 and also frames the serial data transfer.

Multiplexer Select. Logic Input. This input is used to select the pair of channels to be converted

simultaneously, i.e. Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and

ADC B. The logic state of this pin is checked upon the falling edge of CS and the multiplexer is set

up for the next conversion. If it is low, the following conversion will be performed on Channel 1 of

each ADC; if it is high, the following conversion will be performed on Channel 2 of each ADC.

–6–

REV. 0

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