AD7841AS 데이터 시트보기 (PDF) - Analog Devices
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AD7841AS Datasheet PDF : 12 Pages
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AD7841
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero-scale error and full-scale error and is expressed in Least
Significant Bits.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or another of the chan-
nel outputs.
The eight DAC outputs are buffered by op amps that share
common VDD and VSS power supplies. If the dc load current
changes in one channel (due to an update), this can result in a
further dc change in one or another of the channel outputs. This
effect is most obvious at high load currents and reduces as the
load currents are reduced. With high impedance loads the effect
is virtually impossible to measure.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-secs. It is measured with VREF(+) = +5 V and
VREF(–) = –5 V and the digital inputs toggled between 1FFFH and
2000H.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the out-
put of another DAC. It is expressed in dBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that
appears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-secs.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 VREF(+) – 1 LSB.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to 2 VREF(–). Zero-
scale error is mainly due to offsets in the output amplifier.
Gain Error
Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
GENERAL DESCRIPTION
DAC Architecture—General
Each channel consists of a straight 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to twice the
reference span of VREF(+) – VREF(–). The DAC coding is straight
binary; all 0s produces an output of 2 VREF(–); all 1s produces
an output of 2 VREF(+) – 1 LSB.
The analog output voltage of each DAC channel reflects the
contents of its own DAC register. Data is transferred from the
external bus to the input register of each DAC on a per channel
basis.
Bringing the CLR line low switches all the signal outputs, VOUTA
to VOUTH, to the voltage level on the relevant DUTGND pin.
When the CLR signal is brought back high, the output voltages
from the DACs will reflect the data stored in the relevant DAC
registers.
Data Loading to the AD7841
Data is loaded into the AD7841 in straight parallel 14-bit wide
words.
The DAC output voltages, VOUTA – VOUTH are updated to
reflect new data in the DAC registers.
The actual input register being written to is determined by the
logic levels present on the device’s address lines, as shown in
Table I.
Table I. Address Line Truth Table
A2
A1
A0
DAC Selected
0
0
0
INPUT REG A (DAC A)
0
0
1
INPUT REG B (DAC B)
0
1
0
INPUT REG C (DAC C)
0
1
1
INPUT REG D (DAC D)
1
0
0
INPUT REG E (DAC E)
1
0
1
INPUT REG F (DAC F)
1
1
0
INPUT REG G (DAC G)
1
1
1
INPUT REG H (DAC H)
–6–
REV. 0
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