AD7841AS 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
일치하는 목록
AD7841AS Datasheet PDF : 12 Pages
| |||
AD7841
device. Figure 20 shows the recommended capacitor values of
10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high frequen-
cies to handle transient currents due to internal logic switching.
0.1F 10F
VCC
VDD
AD7841
10F 0.1F
VSS
10F 0.1F
Figure 20. Recommended Decoupling Scheme for AD7841
Automated Test Equipment
The AD7841 is particularly suited for use in an automated test
environment. Figure 21 shows the AD7841 providing the neces-
sary voltages for the pin driver and the window comparator in a
typical ATE pin electronics configuration. AD588s are used to
provide reference voltages for the AD7841. In the configuration
shown, the AD588s are configured so that the voltage at Pin 1 is
5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is
5 V less than the voltage at Pin 9.
+15V –15V
VOFFSET
2 16
4
3
6
1
8
15
13 AD588 14
VREF(+)AB
VREF(–)AB
VOUTA
10
11
9
VOUTB
DUTGND_AB
12
0.1F
7
1F
AD7841*
+15V
PIN
DRIVER
–15V
+15V –15V
2 16
4
3
6
1
8
15
13 AD588 14
10
11
9
DUTGND_GH
VOUTG
VREF(+)GH
VREF(–)GH
VOUTH
GND
DEVICE
GND
VOUT
DEVICE
GND
12
7
1F
DEVICE
GND
WINDOW
COMPARATOR
TO TESTER
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. ATE Application
One of the AD588s is used as a reference for DACs A and B.
These DACs are used to provide high and low levels for the pin
driver. The pin driver may have an associated offset. This can
be nulled by applying an offset voltage to Pin 9 of the AD588.
First, the code 1000␣ .␣ .␣ .␣ 0000 is loaded into the DACA latch
and the pin driver output is set to the DACA output. The
VOFFSET voltage is adjusted until 0 V appears between the pin
driver output and DUTGND. This causes both VREF(+) and
VREF(–) to be offset with respect to GND by an amount equal to
VOFFSET. However, the output of the pin driver will vary from
–10 V to +10 V with respect to DUTGND as the DAC input
code varies from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111. The VOFFSET
voltage is also applied to the DUTGND pins. When a clear is
performed on the AD7841, the output of the pin driver will be
0 V with respect to DUTGND.
The other AD588 is used to provide a reference voltage for
DACs G and H. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to Device GND. This causes VREF(+)GH
and VREF(–)GH to be referenced to Device GND. As DAC G
and DAC H input codes vary from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111,
VOUTG and VOUTH vary from –10 V to +10 V with respect to
Device GND. Device GND is also connected to DUTGND.
When the AD7841 is cleared, VOUTG and VOUTH are cleared to
0 V with respect to Device GND.
Programmable Reference Generation for the AD7841 in an
ATE Application
The AD7841 is particularly suited for use in an automated test
environment. The reference input for the AD7841 octal 14-bit
DAC requires three differential references for the eight DACs.
Programmable references may be a requirement in some ATE
applications as the offset and gain errors at the output of a DAC
can be adjusted by varying the voltages on the reference pins of
the DAC. To trim offset errors, the DAC is loaded with the
digital code 000␣ .␣ .␣ .␣ 000 and the voltage on the VREF(–) pin is
adjusted until the desired negative output voltage is obtained.
To trim out gain errors, first the offset error is trimmed. Then
the DAC is loaded with the code 111␣ .␣ .␣ .␣ 111 and the voltage
on the VREF(+) pin is adjusted until the desired full-scale voltage
minus one LSB is obtained.
It is not uncommon in ATE design, to have other circuitry at
the output of the AD7841 that can have offset and gain errors of
up to say ± 300 mV. These offset and gain errors can be easily
removed by adjusting the reference voltages of the AD7841.
The AD7841 uses nominal reference values of ± 5 V to achieve
an output span of ± 10 V. Since the AD7841 has a gain of two
from the reference inputs to the DAC output, adjusting the
reference voltages by ± 150 mV will adjust the DAC offset and
gain by ± 300 mV.
There are a number of suitable 8- and 10-bit DACs available
that would be suitable to drive the reference inputs of the
AD7841, such as the AD7804, a quad 10-bit digital-to-analog
converter with serial load capabilities. The voltage output from
this DAC is in the form of VBIAS ± VSWING and rail-to-rail opera-
tion is achievable. The voltage reference for this DAC can be
internally generated or provided externally. This DAC also
contains an 8-bit SUB DAC which can be used to shift the
complete transfer function of each DAC around the VBIAS point.
This can be used as a fine trim on the output voltage. In this
application two AD7804s are required to provide programmable
reference capability for all eight DACs. One AD7804 is used to
drive the VREF(+) pins and the second package used to drive the
VREF(–) pins.
Another suitable DAC for providing programmable reference
capability is the AD8803. This is an octal 8-bit trimDAC® and
provides independent control of both the top and bottom ends
of the trimDAC. This is helpful in maximizing the resolution of
devices with a limited allowable voltage control range.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. 0
–11–
Share Link: 