PBA31308V2.02SLJYU 데이터 시트보기 (PDF) - Unspecified
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PBA31308V2.02SLJYU Datasheet PDF : 39 Pages
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Intel Public
UniStone
PBA 31308
3.2
PCM Interface
The PCM interface is used to exchange synchronous data (usually audio) between UniStone and the host as well
as to connect e.g. an external audio codec or an external DSP to UniStone. It can be configured as an industry
standard PCM interface supporting long and short frame synchronization, as an I2S interface or as an IOM-2
interface in terminal mode with reduced capabilities.
The main features of the PCM interface are:
• Two bidirectional PCM channels
• Separate supply voltage (VDDPCM) for easy interfacing to other systems
• Support of 16-bit linear samples and 8-bit A-law/μ-law compressed samples as defined in the Bluetooth
specification
• 8 x 32-bit FIFOs for each channel
• Programmable frame length
• Programmable frame signal length
• Programmable channel start positions
• Programmable idle level on PCMOUT
• Programmable low-power/inactive levels on all PCM pins
• Data word LSB justified or MSB justified with respect to frame signal
• Clock master/slave mode
• Frame master/slave mode
• Fractional divider for PCM clock generation
3.2.1 Overview
The PCM interface consists of five signals as shown in Figure 5 below.
PCMCLK
PCMOUT
PCMIN
PCMFR 1
M
S
B
1
4
11
32
1
1
1
0
98
7
6
54
3
2
L
1S
B
M
S
B
1
4
11
32
1
1
1
0
98
7
6
54
3
2
L
1S
B
F rame Signal Length
Data Word Length
IDLE
Don’t Care
M
S
B
1
4
11
32
1
1
1
0
98
7
6
54
3
2
L
1S
B
M
S
B
1
4
11
32
1
1
1
0
98
7
6
54
3
2
L
1S
B
Channel 2 Start Position
F rame Length
IDLE
Don’t Care
M
S
B
1
4
11
32
M
S
B
1
4
11
32
Figure 5 PCM_Signals_Overview
PCM_Interface_ PCM_ Signals_Overview.vsd
The clock signal PCMCLK is the timing base for the other signals in the PCM interface. In clock master mode,
UniStone generates PCMCLK from the internal system clock using a fractional divider. In clock slave mode
PCMCLK is an input to UniStone and has to be supplied by an external source. The maximum PCMCLK frequency
(in both modes) is 1/8 of the internal system clock frequency.
The PCM interface supports up to two bidirectional channels. Data is transmitted on PCMOUT and received on
PCMIN, always with the most significant bit first. 16-bit linear audio samples and 8-bit A-law or μ-law compressed
audio samples are supported.
The samples are organized in frames such that each frame contains one sample in each direction of each active
channel. The frame rate (i.e. sample rate) is controlled by the PCMCLK frequency and the programmable Frame
Length. In the firmware the sample rate has been fixed to 8 kHz. This means that the PCMCLK frequency can be
calculated from Frame Length and does not have to be specified.
Product Overview
17
Revision 1.2, 2009-02-17
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