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Basic Operating Information
UniStone
PBA 31308
Basic Operating Information
2.1
Power Supply
UniStone is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present. The
UniStone chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be accessed from
the VREG pin. This voltage may not be used for supplying other components in the host system but can be used
for referencing the host interfaces.
The PCM interface and the UART interface are supplied with dedicated, independent, reference levels via the
VDDPCM and VDDUART pins. All other digital I/O pins are supplied internally by either 2.5 V (Internal2) or 1.5
V(Internal1). Section 1.4 provides a mapping between pins and supply voltages.
The I/O power domains (VDDPCM and VDDUART) are completely separated from the other power domains and
can stay present also in low power modes.
2.2
Clocking
UniStone has one clock input CLK32 that is optional. If used this 32.768 kHz clock must always be present to
assist UniStone to keep the time in low power modes.
The low power clock can be generated internally by the crystal oscillator and/or the low power oscillator or provided
externally.
Product Overview
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Revision 1.2, 2009-02-17