W83195BG-118 데이터 시트보기 (PDF) - Winbond

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W83195BG-118

Clock Generator

Winbond 

W83195BR-118/W83195BG-118

STEPLESS FOR INTEL 915/945 CHIPSETS

7. I2C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select Register (Default = 10h)

BIT

NAME

PWD

DESCRIPTION

7

SSEL [4]

0 Frequency selection by software via I2C

TYPE

R/W

6

SSEL [3]

0

5

SSEL [2]

0

4

SSEL [1]

1

3

SSEL [0]

0

2

EN_SSEL

0 Enable software frequency table selection SSEL [4:0].

R/W

0 = Select frequency by hardware.

1= Select frequency by software I2C - Bit 7~ 3.

1

SPSPEN

0 Enable Spread Spectrum

R/W

0 = Normal

1 = Spread Spectrum enabled

0 EN_SAFE_FREQ 0 Enable reload safe frequency when the watchdog is timeout. R/W

0 = reload the FS [2:0] latched pins when watchdog time out.

1 = reload the safe frequency bit defined at Register 5 bit 4~0.

7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E2h)

BIT

PIN NO PWD

DESCRIPTION

TYPE

7

Reserve 1 Reserved

R/W

6

40,39

1 CPUT1 / C1 output control

R/W

5

43,42

1 CPUT0 / C0 output control

R/W

4 Reserved 0 Reserved (Read only)

R

3 Reserved 0 Reserved (Read only)

R

2

-

X Power on latched value of FS2 pin, Default: 0 (Read only).

R

1

-

X Power on latched value of FS1 pin, Default: 1 (Read only).

R

0

-

X Power on latched value of FS0 pin, Default: 0 (Read only).

R

-8-

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