VP2612CGGPFR 데이터 시트보기 (PDF) - Mitel Networks

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VP2612CGGPFR

Video Multiplexer

Mitel Networks 

VP2612

START MB

WAIT

(2 cycles)

IS IT

A DUMMY

BLOCK?

no

CONTROL

yes

(2 cycles)

GOB

(2 cycles)

MB

CBP

(2 cycles)

(2 cycles)

QUANT (2 cycles)

HORZ MV (2 cycles)

VERT MV (2 cycles)

ARE

no

ANY BLOCKS

CODED?

yes

WAIT

(32 cycles)

SUB BLK NO (15 cycles)

RUN LENGTH (2 cycles)

MAGNITUDE (2 cycles)

WAIT

(1 cycle)

ARE

ALL COEFFS

no O/P?

yes

WAIT

(wait variable time to make total

time since start of sub-block up

to 335 cycles)

no

ARE

ALL BLOCKS

O/P?

yes

WAIT

(variable cycles)

END MB

Figure 3. DBUS Port Flow Chart

4

Vertical MV : If motion compensation was used the vertical

component of the motion vector will be provided on

DBUS4:0 (DBUS4 is MSB). (This 5 bit value represents a

two's complement number in the range ±15 ( although only

vectors in the range (±7) are currently possible with the

VP2611). If motion compensation was not used this is a

don't care value.

Coded Block Pattern : This byte contains a 6 bit linear code

that indicates which of the sub-blocks actually contain

coded data. DBUS6 will be high if sub-block 1 contains

coded data, through to DBUS1 being high if sub-block 6

contains coded data. DBUS7 and DBUS0 are not used.

Sub-block Number : An identifier for the run length coded

coefficients which are about to be made available.

DBUS2:0 contain the coded sub-block number from 1 to 6.

All zero sub-blocks will not be produced, and their corre-

sponding numbers will not appear.

Zero Run Count : The number of zero valued coefficents

preceding the next non zero coefficient is provided on

DBUS5:0 (DBUS5 is MSB). Normally, DBUS7:6 are low,

except to signify the end of a Sub-block, when they will

both be high. Zero Run Count is always followed by a

coefficient, even at the end of a sub-block.

RLC Coefficient : This byte contains the 8 bit coefficient value.

It will always be a non-zero value, except when the

previous Zero Run Count signalled the end of sub-Block.

A zero value is then possible since, as stated above, the

run count is always followed by a coefficient byte, which

may be zero if the last coefficient is zero.

Wait State : This indicates that no valid data is being output

from the DBUS port during this cycle. No DCLK is pro-

duced for this state.

SYSTEM PROCESSOR INTERFACE

The system processor interface is a memory

mapped microprocessor compatible interface. It has been

designed for use with any system processor, and consists

of the following buses and signals:

HD7:0

HA3:0

WR

RD

CEN

Processor Data Bus

LSBs of address bus

Active Low Write strobe

Active Low Read strobe

Decoded Active Low chip select

Detailed interface timing is shown in Figure 4. Since there

are several internal pipeline registers which are clocked by

SCLK, then access times and strobe widths are dependent

on the period of SCLK.

Table 2 shows the addresses used for each of the user

accessible registers, and the function of each register is

described in detail below.

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