72605L20 데이터 시트보기 (PDF) - Integrated Device Technology
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72605L20 Datasheet PDF : 20 Pages
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IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
Name
I/O
DA0-DA17 Data A
I/O
CSA
Chip Select A
I
R/WA
Read/Write A
I
CLKA
ENA
OEA
Clock A
I
Enable A
I
Output Enable A I
A0, A1, A2 Addresses
I
DB0-DB17 Data B
I/O
R/WB
Read/Write B
I
CLKB
ENB
OEB
Clock B
I
Enable B
I
Output Enable B I
EFAB
A→B Empty Flag O
PAEAB
PAFAB
FFAB
A→B
O
Programmable
Almost-Empty Flag
A→B
O
Programmable
Almost-Full Flag
A→B Full Flag
O
EFBA
B→A Empty Flag O
PAEBA
PAFBA
B→A
O
Programmable
Almost-Empty Flag
B→A
O
Programmable
Almost-Full Flag
Description
Data inputs & outputs for the 18-bit Port A bus.
Port A is accessed when CSA is LOW. Port A is inactive if CSA is HIGH.
This pin controls the read or write direction of Port A. If R/WA is LOW, Data A input data is
written into Port A. If R/WA is HIGH, Data A output data is read from Port A. In bypass mode,
when R/WA is LOW, message is written into A→B output register. If R/WA is HIGH, message
is read from B→A output register.
CLKA is typically a free running clock. Data is read or written into Port A on the rising edge of
CLKA.
When ENA is LOW, data can be read or written to Port A. When ENA is HIGH, no data
transfers occur.
When R/WA is HIGH , Port A is an output bus and OEA controls the high-impedance state of
DA0-DA17. If OEA is HIGH, Port A is in a high-impedance state. If OEA is LOW while CSA is
LOW and R/WA is HIGH, Port A is in an active (low-impedance) state.
When CSA is asserted, A0, A1, A2 and R/WA are used to select one of six internal resources.
Data inputs & outputs for the 18-bit Port B bus.
This pin controls the read or write direction of Port B. If R/WB is LOW, Data B input data is
written into Port B. If R/WB is HIGH, Data B output data is read from Port B. In bypass mode,
when R/WB is LOW, message is written into B→A output register. If R/WB is HIGH, message
is read from A→B output register.
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge
of CLKB.
When ENB is LOW, data can be read or written to Port B. When ENB is HIGH, no data
transfers occur.
When R/WB is HIGH , Port B is an output bus and OEB controls the high-impedance state of
DB0-DB17. If OEB is HIGH, Port B is in a high-impedance state. If OEB is LOW while R/WB
is HIGH, Port B is in an active (low-impedance) state.
When EFAB is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited.
When EFAB is HIGH, the FIFO is not empty. EFAB is synchronized to CLKB. In the bypass
mode, EFAB HIGH indicates that data DA0-DA17 is available for passing through. After the
data DB0-DB17 has been read, EFAB goes LOW.
When PAEAB is LOW, the A→B FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into PAEAB Register. When PAEAB is HIGH, the
A→B FIFO contains more than offset in PAEAB Register. The default offset value for PAEAB
Register is 8. PAEAB is synchronized to CLKB.
When PAFAB is LOW, the A→B FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into PAFAB Register. When PAFAB is HIGH,
the A→B FIFO contains less than or equal to the depth minus the offset in PAFAB Register.
The default offset value for PAFAB Register is 8. PAFAB is synchronized to CLKA.
When FFAB is LOW, the A→B FIFO is full and further data writes into Port A are inhibited.
When FFAB is HIGH, the FIFO is not full. FFAB is synchronized to CLKA. In bypass mode,
FFAB tells Port A that a message is waiting in Port B’s output register. If FFAB is LOW, a
bypass message is in the register. If FFAB is HIGH, Port B has read the message and another
message can be written into Port A.
When EFBA is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited.
When EFBA is HIGH, the FIFO is not empty. EFBA is synchronized to CLKA. In the bypass
mode, EFBA HIGH indicates that data DB0-DB17 is available for passing through. After the
data DA0-DA17 has been read, EFBA goes LOW on the following cycle.
When PAEBA is LOW, the B→A FIFO is almost empty. An almost empty FIFO contains less
than or equal to the offset programmed into PAEBA Register. When PAEBA is HIGH, the
B→A FIFO contains more than offset in PAEBA Register. The default offset value for PAEBA
Register is 8. PAEBA is synchronized to CLKA.
When PAFBA is LOW, the B→A FIFO is almost full. An almost full FIFO contains greater than
the FIFO depth minus the offset programmed into PAFBA Register. When PAFBA is HIGH,
the B→A FIFO contains less than or equal to the depth minus the offset in PAFBA Register.
The default offset value for PAFBA Register is 8. PAFBA is synchronized to CLKB.
2704 tbl 01
5.18
4
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