PCK2010RDL 데이터 시트보기 (PDF) - Philips Electronics
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PCK2010RDL Datasheet PDF : 18 Pages
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Philips Semiconductors
CK98R (100/133MHz) RCC spread spectrum
system clock generator
Product specification
PCK2010R
APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0°C to +70°C
133 MHz MODE
LIMITS
Tamb = 0°C to +70°C
100 MHz MODE
MIN
MAX
MIN
MAX
THKP
THKH
THKL
THRISE
THFALL
TJITTER
DUTY CYCLE
IOAPIC CLK period
IOAPIC CLK HIGH time
IOAPIC CLK LOW time
IOAPIC CLK rise time
IOAPIC CLK fall time
IOAPIC CLK cycle-cycle jitter
IOAPIC CLK Duty Cycle
60.0
25.5
25.3
0.4
0.4
45
64.0
n/a
n/a
1.6
1.6
500
55
60.0
25.5
25.3
0.4
0.4
45
64.0
n/a
n/a
1.6
1.6
500
55
THSKW
IOAPIC CLK pin-pin skew
250
250
UNIT
NOTES
ns
2, 9
ns
5, 10
ns
6, 10
ns
8
ns
8
ps
%
1
ps
2
3V66 CLOCK OUTPUT, 3V66 (0–3) (LUMP CAPACITANCE TEST LOAD = 30 pF)
SYMBOL
PARAMETER
LIMITS
Tamb = 0°C to +70°C
133 MHz MODE
LIMITS
Tamb = 0°C to +70°C
100 MHz MODE
MIN
MAX
MIN
MAX
THKP
THKH
THKL
THRISE
THFALL
TJITTER
DUTY CYCLE
3V66 CLK period
3V66 CLK HIGH time
3V66 CLK LOW time
3V66 CLK rise time
3V66 CLK fall time
3V66 CLK cycle-cycle jitter
3V66 CLK Duty Cycle
15.0
16.0
15.0
16.0
5.25
n/a
5.25
n/a
5.05
n/a
5.05
n/a
0.4
1.6
0.4
1.6
0.4
1.6
0.4
1.6
500
500
45
55
45
55
THSKW
3V66 CLK pin-pin skew
250
250
UNIT
NOTES
ns
2, 9, 4
ns
5, 10
ns
6, 10
ns
8
ns
8
ps
%
1
ps
2
48MHZ(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)
SYMBOL
PARAMETER
f
fD
THRISE (tR)
THFALL (tF)
DUTY CYCLE (tD)
Frequency, Actual
Deviation from 48 MHz
Output rise edge rate
Output fall edge rate
Duty Cycle
TJITTER
CLK cycle-cycle jitter
THSTB (fST)
Frequency stabilization from Power-up (cold start)
NOTE:
1. See Figure 5 for measure points.
TEST CONDITIONS
NOTES
Determined by PLL
divider ratio
(48.008 – 48)/48
133 MHz
MIN
MAX
500
LIMITS
Tamb = 0°C to +70°C
MIN
MAX
48.008
+167
1
4
1
4
45
55
100 MHz
MIN
MAX
500
3
UNIT
MHz
ppm
ns
ns
%
ps
ms
1999 Oct 19
9
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