PCK2010RDL 데이터 시트보기 (PDF) - Philips Electronics
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PCK2010RDL Datasheet PDF : 18 Pages
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Philips Semiconductors
CK98R (100/133MHz) RCC spread spectrum
system clock generator
Product specification
PCK2010R
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2,3
REF [0–1]
3.3 V 14.318 MHz clock output
5
XTAL_IN
14.318 MHz crystal input
6
XTAL_OUT
14.318 MHz crystal output
8
PCICLK_F
3.3 V free running PCI clock
9, 11, 12, 14, 15, 17, 18
PCICLK [1–7]
3.3 V PCI clock outputs
21, 22, 25, 26
3V66 [0–3]
3.3 V fixed 66 MHz clock outputs
28
SEL133/100
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
H = 133 MHz, L = 100 MHz
30
48 MHz USB
3.3 V fixed 48 MHZ clock output
32, 33
SEL [0–1]
Logic select pins. TTL levels.
34
SPREAD
3.3 V LVTTL input. Enables spread spectrum mode when held LOW.
35
PWRDWN
3.3 V LVTTL input. Device enters powerdown mode when held LOW.
36
CPUSTOP
3.3 V LVTTL input. Stops all CPU clocks and 3V66 clocks when held LOW. CPUDIV_2
output remains on all the time.
37
PCISTOP
3.3 V LVTTL input. Stops all PCI clocks except PCICLK_F when held LOW.
41, 42, 45, 46
CPUCLK [0–3]
2.5 V CPU output. 133 MHz or 100MHz depending on state of input pin SEL133/100.
49, 50
CPUDIV_2 [0–1]
2.5 V output running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on
state of input pin SEL133/100.
53, 54, 55
IOAPIC [0–2]
2.5 V clock outputs running divide synchronous with the CPU clock frequency. Fixed
16.67 MHz limit.
4, 10, 16, 23, 27, 31, 39
1, 7, 13, 19, 20, 24, 29,
38, 40, 44, 48, 52
VDD3V
VSS
3.3 V power supply.
Ground
43, 47, 51, 56
VDD25V
2.5 V power supply
NOTE:
1. VDD3V, VDD25V and VSS in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise
on the performance of the device. In reality, the platform will be configured with the VDD25V pins tied to a 2.5 V supply, all remaining VDD pins
tied to a common 3.3 V supply and all VSS pins being common.
1999 Oct 19
3
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