TC58NVG0S3AFT05 데이터 시트보기 (PDF) - Toshiba

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TC58NVG0S3AFT05

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

AC TEST CONDITIONS

TC58NVG0S3AFT05

PARAMETER

Input level

Input pulse rise and fall time

Input comparison level

Output data comparison level

Output load

CONDITION

2.4 V, 0.4 V

3 ns

1.5 V, 1.5 V

1.5 V, 1.5 V

CL (100 pF) + 1 TTL

PROGRAMMING AND ERASING CHARACTERISTICS

(Ta = 0 to 70°C, VCC = 2.7 V~3.6 V)

SYMBOL

PARAMETER

MIN

tPROG

Average Programming Time



N

Number of Programming Cycles on Same Page

(per 512 + 16 bytes)



tBERASE

Block Erasing Time



(1) Refer to Application Note (12) toward the end of this document.

TYP.

200



2

MAX

700

2

4

UNIT

µs

ms

NOTES

(1)

2003-08-20A 5/33

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