TC58NVG0S3AFT05 데이터 시트보기 (PDF) - Toshiba

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TC58NVG0S3AFT05

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Toshiba 

Table 3. Command table (HEX)

Serial Data Input

Auto Program

Read Address Input

Column Address Change in Serial Data Output

Read Start

Read Column Change

Auto Block Erase

ID Read

Status Read

Reset

First Cycle

80

10

00

05

30

E0

60

90

70

FF

TC58NVG0S3AFT05

Second Cycle











D0



Acceptable while Busy

○

○

HEX data bit assignment

(Example)

Serial Data Input: 80h

10000000

I/O8 7 6 5 4 3 2 I/O1

Table 4. shows the operation states for Read mode.

Table 4. Read mode operation states

CLE

ALE

CE

WE

RE

I/O1 to I/O8

Power

Output select

L

L

L

H

L

Data output

Active

Output Deselect

L

L

L

H

H

High impedance

Active

Standby

L

L

H

H

*

High impedance

Standby

Read Busy

*

*

*

*

*

High Impedance

Active

H: VIH, L: VIL, *: VIH or VIL

2003-08-20A 17/33

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