U62H824PA
Read Cycle 1: Ai- or V/S-controlled (during Read Cycle: E1 = G = VIL, E2 = W = VIH)
Ai
DQi
Output
V/S
DQi
Output
Previous
Data Valid
Previous
Data Valid
tcR
Address Valid
ta(A )
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Output Data
Valid
tv(A)
tcR
MUX Control Valid
ta(V S)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Output Data
Valid
tv(VS)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Read Cycle 2: E-, G-controlled (during Read Cycle: W = VIH)
E1 in the timing diagrams represents both E1 and E2 with E1 asserted Low and E2 asserted High.
Ai
V/S
E1
G
DQi
Output
tcR
Address Valid
MUX Control Valid
ten(E)
ta(E)
ten(G)
ta(G)
tdis(E)
tdis(G)
High-Z
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Output Data
Valid
High-Z
December 12, 1997
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