U62H824PA35 데이터 시트보기 (PDF) - Zentrum Mikroelektronik Dresden AG
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U62H824PA35 Datasheet PDF : 10 Pages
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U62H824PA
Automotive Fast 8K x 24 SRAM
Features
F 196 608 bit static CMOS RAM
F 35 ns Access Time
F Fully static Read and Write
F operations
Equal address and chip
F enable access times
Single bit on-chip address
F multiplexer
Active high and active low
F chip enable inputs
Output enable controlled three-
state outputs
F TTL/CMOS-compatible
F Low power standby mode
F Power supply voltage 5 V
F Operating temperature range
-40 °C to 125 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity > 100 mA
F Package: PLCC52
Description
The U62H824PA is a static RAM
manufactured using a CMOS pro-
cess technology. The device inte-
grates an 8K x 24 SRAM core with
multiple chip enable inputs, output
enable, and an externally control-
led single address pin multiplexer.
These functions allow for direct
connection to the Motorola
DSP56k Digital Signal Processor
Family and provide a very efficient
means for implementation of a
reduced parts count system requi-
ring no additional interface logic.
The avialability of multiple chip
enable (E1 and E2) and output
enable (G) inputs provides for
greater system flexibility when mul-
tiple devices are used. With either
chip enable unasserted, the device
will enter standby mode, useful in
low-power applications. A single
on-chip multiplexer selects A12 or
X/Y as the highest order address
input depending upon the state of
the V/S control input. This feature
allows one physical static RAM
component to efficiently store pro-
gram and vector or scalar ope-
rands by dynamically re-
partitioning the RAM array.
Typical applications will logically
map vector operands into upper
memory with scalar operands
being stored in lower memory.
An application example is at the
end of this document for additional
information.
Multiple power and ground pins
have been utilized to minimize
effectes induced by output noice.
Pin Configuration
Pin Description
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
DQ14
DQ13
Signal Name Signal Description
A0 - A11
A12, X/Y
V/S
DQ0 - DQ23
E1, E2
G
W
VCC
VSS
NC
Address Inputs
Multiplexed Address
Address Multiplexer Control
Data Input / Output
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Not Connected
For proper operation of the device, all VSS pins
must be connected to ground.
December 12, 1997
1
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