NCP1380 데이터 시트보기 (PDF) - ON Semiconductor
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NCP1380
ON Semiconductor
NCP1380 Datasheet PDF : 26 Pages
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NCP1380
VDD
R pul l up
FB
VDD
LOGIC BLOCK
VDD
BO reset
latch V CC management
fa ul t
gr a nd
reset
VCCstop
aux
VCC
VDD
clamp
Ct
ZCD
La ux
CS
Rsense
ICt
+
Ct se tpoint −
DRV
gr a nd
reset
R
DRV
ga te
Ct
discharge
+
10 V
ESD
−
Vth
DRV
3 ms blanking
de ma g
SS end
40 ms
Time Out
/4
The 40 ms Time Out is active
only during s oft−s ta r t
SS end
5 ms
Time Out
Ipeak(VCO) = 17.5% VILIMIT
S
Q
Q
R
P W Mreset
Q
QS
C:
l a tc he d
CsS top
GN D
Up
TIMER
Down
Res et
I pFl a g
P W Mreset
gr a nd
reset
nois e de la y
+
−
VOVP
VCC HV
LEB 1
OPP
IpFlag
VILIMIT
LEB 2
LEB 2 is shorter than LEB 1
+
Soft-start
−
Soft−s ta r t e nd ? the n 1
else 0
SS end
+
CsS top
−
VCS ( st op)
noi s e de l a y
BO r es et
VDD
IBO
OVP/BO
VBO
+
−
Rclamp
Vclamp
Figure 4. Internal Circuit Architecture for Versions C and D
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