NCP1380 데이터 시트보기 (PDF) - ON Semiconductor
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NCP1380
ON Semiconductor
NCP1380 Datasheet PDF : 26 Pages
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NCP1380
INTERNAL CIRCUIT ARCHITECTURE
VDD
Rpullup
FB
VDD
L OGI C BL OCK
VDD
BO r eset
latch V CC management
fa ul t
gr a nd
reset
VCCstop
aux
VCC
VDD
ICt
Ct
+
Ct s e tpoi nt −
DRV
ZCD
La ux
CS
Rsense
Ct
Discharge
+
10 V
ESD
−
Vth
DRV
3 ms blanking
de ma g
S
Q
Q
SS end
/4
SS end
Ipeak(VCO) = 17.5% VILIMIT
40 ms
Ti me Out
The 40 ms Time Out is active
only during s oft−s ta r t
5 ms
Ti me Out
R
PWMreset
LEB 1
OPP
IpFlag
VILIMIT
LEB 2
LEB 2 is shorter than LEB 1
+
Soft- s tar t
−
Soft−s ta rt e nd ? the n 1
else 0
SS end
CsS top
+
−
VC S(stop)
gr a nd
reset
R
Q
QS
A:
l a tc he d
clamp
DRV
ga te
Cs S top
GN D
IpFlag
P W Mr eset
Up
TIM ER
Down
Reset
gr a nd
reset
noi s e de l a y
VOVP
VDD
IOTP(REF)
VCC
Fa ul t
noi s e de l a y
SS end
VOTP
Figure 3. Internal Circuit Architecture for Versions A and B
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