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MV1442DPAS

HDB3 Encoder/Decoder/Clock Regenerator

Zarlink Semiconductor Inc 

MV1442

RXD1

RXD2

DECODER

CLOCK

LOSS OF

INPUT

1 2 3 4 5 6 7 8 9 10 11

1 CLOCK PERIOD

NOTE

The LOSS OF INPUT output is delayed by one clock period with respect to the incoming HDB3 waveform

Figure 6 - Loss of input waveforms

DECODER

CLOCK

NRZ DATA OUT

RESET AIS

AIS

Figure 7 - AIS and RESET AIS waveforms

Pin

Signal name

Description

1

NRZ DATA IN

Input pin for data to be encoded into pseudo-ternary HDB3 form. This data is clocked into

the Encoder block by the falling edge of ENCODER CLOCK.

2 ENCODER CLOCK Clock input for the encoding of data on pin 1.

3

LOSS OF INPUT

Output from the loss of input circuit This output goes high one clock period after the

detection of eleven consecutive zeros on the decoder inputs. Any logic ‘1’ at the input

(RXD1 or RXD2=0) resets this count after a single clock period delay.

4

NRZ DATA OUT

NRZ data output obtained from the decoding of the pseudo-ternary inputs to the Decoder

block.

5 DECODER CLOCK Clock input to the Decoder block for decoding data on RXD1 and RXD2 or TXD1 and TXD2

in loop test mode. In internal clock regeneration mode, this pin is used to output the

regenerated clock to external circuitry. In external clock regeneration, mode this pin is

used to input the externally regenerated clock signal direct to the Decoder block.

6

RESET AIS

Reset input to the decoded zero counter A logic ‘0’ on this input resets a decoded zero

counter. It will also reset the AIS output to ‘0’ provided 3 or more zeros have been decoded

in the preceding RESET AIS = 1 period or set AIS to 1 if less than 3 zeros have been

decoded in the preceding RESET AIS = 1 period This may be used to indicate loss of

timeslot zero. A logic ‘1’ on this pin enables the decoded zero counter.

7

AIS

Output from AIS circuit (see description for pin 6).

8

MODE

Input pin for selection of clock regeneration mode. A logic high on this input selects internal

crystal controlled clock regeneration while a logic low selects external clock regeneration.

9

GND

Digital ground 0V.

Table 1 - Pin descriptions

Contd…

4

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