MV1442DPAS 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MV1442DPAS Datasheet PDF : 12 Pages
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MV1442
absence of input jitter the MV1442 will produce an output
jitter waveform in the form of a sawtooth ramping between
0UI and 0.125UI. The period of this waveform will be de-
pendent upon the difference in frequencies between the
remote transmitter’s clock and the crystal controlled clock of
the MV1442.
The MV1442 was originally designed as a pin compatible
replacement for the MV1441 with a much improved internal
clock recovery circuit and allowing operation at 8.448MHz
with external clock recovery selected.
ENCODER
CLOCK
NRZ DATA IN
4·5 CLOCK PERIODS
TXD1
B
B
B
V
TXD2
B
B
V
NOTES
1. The encoded HDB3 outputs, TXD1 and TXD2. are delayed dy 4·5 clock periods with respect to NRZ DATA IN.
2. B is an HDB3 mark, V is an HDB3 violation.
Figure 3 - Encoder waveforms
RXD1
RXD2
CDR
B
B
B
V
B
B
B
B
B
B
DECODER
CLOCK
NRZ DATA OUT
5 CLOCK PERIODS
NOTES
1. The decoded NRZ output is delayed by 5 clock periods with respect to the HDB3 inputs.
2. The diagram assumes the last violation occured on RXD2.
3. B is an HDB3 mark, V is an HDB3 violation.
Figure 4 - Decoder waveforms
RXD1
B
B
V
BV
V
RXD2
B
B
B
DECODER
CLOCK
DOUBLE
VIOLATION
1 CLOCK PERIOD
NOTES
1. There is a single clock period delay from detection of an error and the rising edge of DOUBLE VIOLATION
2. The diagram assumes the last violation occured on RXD2.
3. B is an HDB3 mark, V is an HDB3 violation.
Figure 5 - HDB3 double violation waveforms
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