MT9046(2003) 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

Data Sheet

MT9046

All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of

Operation section for full details.

To

Reference

Select MUX

To TIE

Corrector

Enable

To DPLL

State

Select

RSEL

Control

State Machine

PCCi

MS1

MS2

Figure 6 - Control State Machine Block Diagram

Master Clock

The MT9046 can use either a clock or crystal as the master timing source. For recommended master timing

circuits, see the Applications - Master Clock section.

Control and Mode of Operation

The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2.

RSEL

Input Reference

0

PRI

1

SEC

Table 2 - Input Reference Selection

MS2 MS1

Mode

0

0

NORMAL

0

1

HOLDOVER

1

0

FREERUN

1

1

Reserved

Table 3 - Operating Modes and States

The MT9046 has three possible modes of operation, Normal, Holdover and Freerun.

As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control. Refer to

Table 4 and Figure 7 for details of the state change sequences.

Normal Mode

Normal Mode is typically used when a slave clock source, synchronized to the network is required.

In Normal Mode, the MT9046 provides timing (C1.5o, C2o, C4o, C8o, C16o and C19o) and frame

synchronization (F0o, F8o, F16o, TSP and RSP) signals, which are synchronized to one of two reference inputs

Zarlink Semiconductor Inc.

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