MT9046(2003) 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

Data Sheet

MT9046

Pin Description (continued)

Pin #

8

9

11

12

13

14

15

16

18

19

20

21

22

24

25

26

27

29

30

32

Name

Description

OSCo

OSCi

F16o

F0o

Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is

connected from this pin to OSCi, see Figure 9. For clock oscillator operation, this pin is left

unconnected, see Figure 8.

Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is

connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is

connected to a clock source, see Figure 8.

Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low framing

pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS

operation at 8.192 Mb/s. See Figure 14.

Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low framing

pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS

operation at 2.048Mb/s and 4.096Mb/s. See Figure 14.

RSP

Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,

which marks the beginning of an ST-BUS frame. This is typically used for connection to the

Siemens MUNICH-32 device. See Figure 15.

TSP Transmit Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing pulse,

which marks the beginning of an ST-BUS frame. This is typically used for connection to the

Siemens MUNICH-32 device. See Figure 15.

F8o Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse, which marks

the beginning of a frame. See Figure 14.

C1.5o Clock 1.544MHz (CMOS Output). This output is used in T1 applications.

LOCK

C2o

C4o

Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to

the input reference.

Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.

Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s

and 4.096Mb/s.

C19o Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications.

FLOCK

IC

C8o

C16o

C6o

HOLD

OVER

Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference

(less than 500 ms locking time).

Internal Connection. Tie low for normal operation.

Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.

Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a

16.384MHz clock.

Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.

Holdover (CMOS Output). This output goes to a logic high whenever the PLL goes into

holdover mode.

PCCi

Phase Continuity Control Input (Input). The signal at this pin affects the state changes

between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and

Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o.

See Table 4.

NC No connection. Leave open circuit

Zarlink Semiconductor Inc.

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