MT9046(2003) 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

MT9046

Data Sheet

Tapped

Delay

Line

T1 Divider

12MHz

C1.5o

From

DPLL

Tapped

Delay

Line

E1 Divider

16MHz

Tapped

Delay

Line

12MHz DS2 Divider

C2o

C4o

C8o

C16o

F0o

F8o

F16o

C6o

Tapped

Delay

Line

19MHz

C19o

Figure 5 - Output Interface Circuit Block Diagram

The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.

The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock

outputs are locked to one another for all operating states, and are also locked to the selected input reference in

Normal Mode. See Figures 14 & 16.

All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high

capacitance (e.g., 30pF) loads.

Input Impairment Monitor

This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover)

when the frequency of the incoming signal is outside the Auto-Holdover capture range. (See AC Electrical

Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in

the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the

output signal locked to the input signal. The holdover output signal in the MT9046 is based on the incoming

signal 30ms minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover

is negligible because the Holdover Mode is very accurate (e.g., ±0.2ppm). Consequently, the phase delay

between the input and output after switching back to Normal Mode is preserved.

State Machine Control

As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the

DPLL. Control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6).

When switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1,

and disabled when PCCi = 0.

8

Zarlink Semiconductor Inc.

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