MT9045 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9045

T1/E1/OC3 System Synchronizer

Zarlink Semiconductor Inc 

MT9045

Data Sheet

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure

5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,

and a DS2 Divider Circuit to generate the required output signals.

Four tapped delay lines are used to generate 16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.

The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs.

The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.

These outputs have a nominal 50% duty cycle.

The T1 Divider Circuit uses the 12.384MHz signal to generate the C1.5o clock by dividing the internal C12 clock

by eight. This output has a nominal 50% duty cycle.

The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal

50% duty cycle.

Tapped

Delay

Line

T1 Divider

12MHz

C1.5o

From

DPLL

Tapped

Delay

Line

E1 Divider

16MHz

Tapped

Delay

Line

12MHz DS2 Divider

C2o

C4o

C8o

C16o

F0o

F8o

F16o

C6o

Tapped

Delay

Line

19MHz

C19o

Figure 5 - Output Interface Circuit Block Diagram

The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.

The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs

are locked to one another for all operating states, and are also locked to the selected input reference in Normal

Mode. See Figures 14 & 16.

All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high

capacitance (e.g., 30pF) loads.

8

Zarlink Semiconductor Inc.

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