MT9045 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT9045

T1/E1/OC3 System Synchronizer

Zarlink Semiconductor Inc 

MT9045

Data Sheet

PRI or SEC

from

Reference

Select Mux

Programmable

Delay Circuit

TCLR

Resets Delay

Control

Circuit

Control Signal

Delay Value

Compare

Circuit

Virtual

Reference

to DPLL

TIE Corrector

Enable

from

State Machine

Feedback

Signal from

Frequency

Select MUX

Figure 3 - TIE Correction Circuit

As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the

signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is

input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.

During a switch from one reference to the other, the State Machine first changes the mode of the device

from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an

accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the

current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the

Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as

the previous reference signal would have been if the reference switch not taken place. The State Machine then

returns the device to Normal Mode.

The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,

no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change

at the input of the DPLL, or at the output of the DPLL.

Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual

reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.

This phase error is a function of the difference in phase between the two input reference signals during reference

rearrangements. Each time a reference switch is made, the delay between input signal and output signal will

change. The value of this delay is the accumulation of the error measured during each reference switch.

The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A

minimum reset pulse width is 300ns. This results in a phase alignment between the input reference signal and the

output signal as shown in Figure 14. The speed of the phase alignment correction is limited to 5ns per 125us, and

convergence is in the direction of least phase travel.

The state diagram of Figure 7 indicates which state changes the TIE Corrector Circuit is activated.

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Zarlink Semiconductor Inc.

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