MSM7584D 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM7584D Datasheet PDF : 58 Pages
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¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
VAIN
VDIN
TSTG
Condition
—
—
—
—
FEDL7584D-02
MSM7584D
Rating
–0.3 to +5
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–55 to +150
Unit
V
V
V
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature Range
Symbol
VDD
Ta
Conditon
—
High Level Input Voltage
VIH Input pins fully digital
Low Level Input Voltage
Digital Input Rise Time
Digital Input Fall Time
Digital Output Load
VIL Input pins fully digital
tIr Input pins fully digital
tIf Input pins fully digital
RDL IS (Pull-up resistor)
CDL Input pins fully digital
(VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C)
Min. Typ. Max. Unit
2.7
—
3.6
V
–25
+25
+70
°C
0.45 ¥
—
VDD
VDD
V
0.16 ¥
0
—
V
VDD
—
—
50
ns
—
—
50
ns
500
—
—
W
—
—
100
pF
Bypass Capacitor for SG
CSG1 Between SGCT/R and AGC
10 + 0.1 —
—
mF
Bypass Capacitor for SG
Between SGM, AGM and SGRS,
CSG2 AGM
Master Clock Frequency
FMCK MCK
Master Clock Duty Ratio
DMCK MCK
Modulator Side Input
FTXC1 TXCI (When CR14 - B6 = "0")
Frequency
FTXC2 TXCI (When CR14 - B6 = "1")
Clock Duty Ratio
DCKM TXCI, EXCK
IF Input Duty Ratio
DCIF IFIN
Transmit Sync Pulse
Setting Time
tXSM, tSXM TXCI´TXW
tDSM, tDHM TXCI´TXD
Fig.10
Bit Clock Frequency
FBCK BCLK
Synchronous Signal Frequency FSYNC SYNC, SYNC
Clock Duty Ratio
DCKC BCLK, EXCK
Transmit Sync Pulse Setting Time tXSC, tSXC BCLK´SYNC
Receive Sync Pulse Setting Time tRSC, tSRC BCLK´SYNC
Synchronous Signal Width tWSC XSYNC, SYNC
Fig.8
PCM, ADPCM Setup Time tDSC
—
PCM, ADPCM Hold Time
tDHC
—
0.1
—
40
—
—
40
45
—
—
64
—
40
100
100
1 BCLK
100
100
—
—
mF
19.2
— MHz
50
60
%
384
—
kHz
3.84
— MHz
50
60
%
50
55
%
—
200
ns
—
200
ns
—
2048 kHz
8.0
—
kHz
50
60
%
—
—
ns
—
—
ns
— 125ms-1BCLK ms
—
—
ns
—
—
ns
20/58
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