MSM7584D 데이터 시트보기 (PDF) - Oki Electric Industry
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MSM7584D Datasheet PDF : 58 Pages
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¡ Semiconductor
FEDL7584D-02
MSM7584D
VDDM
+3 V power supply for the modem unit.
Connect this pin to the ADPCM CODEC power supply VDDC on the board.
AGM
Modem analog signal ground.
DGM
Modem digital signal ground.
Since this pin is internaly separated from AGM, AGC, and DGC, this pin must be connected to
theses pins on the board.
MCK
Master clock input. The clock frequency is 19.2 MHz.
The master clock must always be input to the ADPCM CODEC and MODEM except the device
being in power down mode because the both units share the master clock.
If the input level is less than 2 V, the master clock must be input after DC-component is cut by
an approx. 1000 pF capacitor. (See the application circuit example.)
IFIN
Modulated signal input for the demodulator unit.
The CR14 - B4 can select an IF frequency of 1.2 MHz or 10.8 MHz.
RXD, RXC, RXSC
Receive data, receive clock (384 kHz), receive symbol clock (192 kHz) outputs.
When the power is turned on, outputs in which a clock regeneration circuit selected by SLS
appear on these output pin.
RXD
RXC
RXSC
SLS
1 Symbol
The regenerated data and clock are
selected asynchronously by the SLS signal.
Figure 4 Timing Diagram of RXD, RXC, and RXSC
SLS
Receive side operation slot selection signal.
This device has two clock regeneration circuits and two AFC data memory registers. If SLS is at
"0" level, slot 1 is selected; if SLS is at "1" level, slot 2 is selected.
RPR
High-speed phase clock control signal input for the clock regeneration circuit.
If this pin is at "1" level, the clock regeneration circuit enters the high-speed phase clock mode.
When the phase difference is less than a defined value, the circuit shifts to the low-speed phase
clock mode automatically. If this pin is at "0" level, the circuit is always in the low-speed phase
clock mode.
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