MCP40D17-103AE 데이터 시트보기 (PDF) - Microchip Technology
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MCP40D17-103AE
Microchip Technology
MCP40D17-103AE Datasheet PDF : 66 Pages
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MCP40D17/18/19
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Parame- Sym Characteristic
ter No.
Min
Max Units
Conditions
100
101
102A ( 5)
102B ( 5)
103A ( 5)
103B ( 5)
THIGH
TLOW
TRSCL
TRSDA
TFSCL
TFSDA
Clock high time
Clock low time
SCL rise time
SDA rise time
SCL fall time
SDA fall time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4000
600
4700
1300
—
20 + 0.1Cb
—
20 + 0.1Cb
—
20 + 0.1Cb
—
20 + 0.1Cb
( 4)
—
—
—
—
1000
300
1000
300
300
40
300
300
ns 1.8V-5.5V
ns 2.7V-5.5V
ns 1.8V-5.5V
ns 2.7V-5.5V
ns Cb is specified to be from
ns 10 to 400 pF
ns Cb is specified to be from
ns 10 to 400 pF
ns Cb is specified to be from
ns 10 to 400 pF
ns Cb is specified to be from
ns 10 to 400 pF
106
107
109
110
Note 1:
2:
3:
4:
5:
6:
THD:DAT Data input hold 100 kHz mode
0
time
400 kHz mode
0
—
ns 1.8V-5.5V, Note 6
—
ns 2.7V-5.5V, Note 6
TSU:DAT Data input
100 kHz mode
250
setup time
400 kHz mode
100
—
ns ( 2)
—
ns
TAA Output valid
from clock
100 kHz mode
400 kHz mode
—
3450 ns ( 1)
—
900 ns
TBUF Bus free time
100 kHz mode
400 kHz mode
4700
1300
—
ns Time the bus must be free
—
ns before a new transmission
can start
TSP Input filter spike 100 kHz mode
—
suppression
400 kHz mode
—
(SDA and SCL)
50 ns Philips Spec states N.A.
50 ns
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
The MCP40D18/MCP40D19 device must provide a data hold time to bridge the undefined part between
VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to guarantee that the output data will meet the setup and hold specifications for the
receiving device.
Use Cb in pF for the calculations.
Not Tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
DS22152B-page 10
© 2009 Microchip Technology Inc.
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