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MCP3911

3.3V Two-Channel Analog Front End

Microchip Technology 

MCP3911

TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V, MCLK = 4 MHz;

PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, AZ_FREQ = 0, DITHER<1:0> = 11, BOOST<1:0> = 10;

VCM = 0V; TA = -40°C to +125°C; VIN = 1.2VPP = 424 mVRMS at 50/60 Hz on both channels.

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Integral Non-Linearity

INL

5

ppm

Differential Input

Impedance

ZIN

232

—

—

kΩ G = 1,

proportional to 1/AMCLK

142

—

—

kΩ G = 2,

proportional to 1/AMCLK

72

—

—

kΩ G = 4,

proportional to 1/AMCLK

38

—

—

kΩ G = 8,

proportional to 1/AMCLK

36

—

—

kΩ G = 16,

proportional to 1/AMCLK

33

—

—

kΩ G = 32,

proportional to 1/AMCLK

Signal-to-Noise

and Distortion Ratio

(Note 1)

SINAD

92

94.5

—

dB

Total Harmonic Distortion

(Note 1)

THD

—

-106.5 -103

dBc Includes the first

35 harmonics

Signal-to-Noise Ratio

(Note 1)

SNR

92

95

—

dB

Spurious Free

Dynamic Range (Note 1)

SFDR

—

111

—

dBFS

Crosstalk (50, 60 Hz)

CTALK

—

-122

—

dB

AC Power

Supply Rejection

DC Power

Supply Rejection

AC PSRR

DC PSRR

—

-73

—

—

-73

—

dB AVDD = DVDD = 3.3V+0.6VPP

, 50/60 Hz, 100/120 Hz

dB AVDD = DVDD = 2.7V to 3.6V

DC Common Mode

Rejection

DC CMRR

—

-105

—

dB VCM from -1V to +1V

Note 1:

2:

3:

4:

5:

6:

This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or

instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range,

VIN = 1.2VPP = 424 mVRMS, VREF = 1.2V at 50/60 Hz. See Section 4.0, Terminologies And Formulas for definition.

This parameter is established by characterization and not 100% tested. See performance graphs for other than default

settings provided here.

For these operating currents, the following configuration bit settings apply: SHUTDOWN<1:0> = 00,

RESET<1:0> = 00, VREFEXT = 0, CLKEXT = 0.

For these operating currents, the following configuration bit settings apply: SHUTDOWN<1:0> = 11, VREFEXT = 1,

CLKEXT = 1.

Applies to all gains. Offset and gain errors depend on PGA gain setting, see Section 2.0, Typical Performance

Curves for typical performance.

Outside of this range, the ADC accuracy is not specified. An extended input range of ±2 V can be applied continuously

to the part with no damage.

For proper operation and optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in

Table 5-2 as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the prescaler

settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.

DS20002286C-page 4

 2012-2013 Microchip Technology Inc.

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