MCF5211(2006) 데이터 시트보기 (PDF) - Freescale Semiconductor

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MCF5211
(Rev.:2006)

Microcontroller Family Hardware Specification

Freescale Semiconductor 

MCF5213 Family Configurations

1.2.14 Pulse Width Modulation Timers

The MCF5213 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty

cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms

with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and

can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle

resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a

single 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit

channels.

1.2.15 Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter

is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must

periodically restart the countdown.

1.2.16 Phase Locked Loop (PLL)

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked

loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control

logic. In order to improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their

own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply

pins, VDD and VSS.

1.2.17 Interrupt Controller (INTC)

The MCF5213 has a single interrupt controller that supports up to 63 interrupt sources. There are 56

programmable sources, 49 of which are assigned to unique peripheral interrupt requests. The remaining 7

sources are unassigned and may be used for software interrupt requests.

1.2.18 DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with

minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line

transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the

occurrence of certain UART or DMA timer events.

1.2.19 Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and

keeps track of what caused the last reset. There are seven sources of reset:

• External reset input

• Power-on reset (POR)

• Watchdog timer

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Freescale Semiconductor

Preliminary

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