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MCF5211
(Rev.:2006)

Microcontroller Family Hardware Specification

Freescale Semiconductor 

MCF5213 Family Configurations

1.2.10 Fast ADC

The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold

(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible

buffers for further processing.

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or

perform a programmed scan sequence repeatedly until manually stopped.

The ADC can be configured for either sequential or simultaneous conversion. When configured for

sequential conversions, up to eight channels can be sampled and stored in any order specified by the

channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same

time. This configuration requires that a single channel may not be sampled by both S/H circuits

simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures

below the low threshold limit or above the high threshold limit set in the limit registers) or at several

different zero crossing conditions.

1.2.11 DMA Timers (DTIM0–DTIM3)

There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3)

on the MCF5213. Each module incorporates a 32-bit timer with a separate register set for configuration

and control. The timers can be configured to operate from the system clock or from an external clock

source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The

input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter

register (TCRn). Each of these timers can be configured for input capture or reference (output) compare

mode. Timer events may optionally cause interrupt requests or DMA transfers.

1.2.12 General Purpose Timer (GPT)

The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter

driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input capture

or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit

range of the counter. The input capture and output compare functions allow simultaneous input waveform

measurements and output waveform generation. The input capture function can capture the time of a

selected transition edge. The output compare function can generate output waveforms and timer software

delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular

intervals with minimal processor intervention. Each timer can either count down from the value written in

its PIT modulus register, or it can be a free-running down-counter.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

12

Preliminary

Freescale Semiconductor

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