MCF5211(2006) 데이터 시트보기 (PDF) - Freescale Semiconductor

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MCF5211
(Rev.:2006)

Microcontroller Family Hardware Specification

Freescale Semiconductor 

MCF5213 Family Configurations

voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory

controller which supports interleaved accesses from the 2-cycle Flash arrays. A backdoor mapping of the

Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath

for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming

interface that allows the Flash to be read, erased and programmed by an external controller in a format

compatible with most SPI bus Flash memory chips.

1.2.5 Power Management

The MCF5213 incorporates several low power modes of operation which are entered under program

control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors

the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD)

monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the

LVD trip point. The RAM standby switch provides power to RAM when the supply voltage to the chip

falls below the standby battery voltage.

1.2.6 FlexCAN

The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts

A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific

requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of

FlexCAN has 16 message buffers.

1.2.7 UARTs

The MCF5213 has three full-duplex UARTs that function independently. The three UARTs can be clocked

by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third

UART is multiplexed with other digital I/O functions.

1.2.8 I2C Bus

The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange

and minimizes the interconnection between devices. This bus is suitable for applications requiring

occasional communications over a short distance between many devices.

1.2.9 QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with

queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU

intervention between transfers.

MCF5213 Microcontroller Family Hardware Specification, Rev. 1.2

Freescale Semiconductor

Preliminary

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