Quick-PWM Slave Controller with
Driver Disable for Multiphase DC-DC Converter
SLAVE
CONTROLLER
ILIM
MAX1980
LIMIT
RC
CREF
RD
RA
RLIMIT
CLIMIT
RB
MASTER
CONTROLLER
REF
MAX1718
ILIM
VITHM(HIGH)
=
1
10
RB
RA + RB
VREF
( ) VITHM(LOW)
=
1
10
RA
RB //RLIMIT
+ RB //RLIMIT
VREF
VITHS
=
1
10
RD
RC + RD
VREF
Figure 5. Setting the Adjustable Current Limits
where VITHM, the master’s current-limit threshold, is typ-
ically 1/10th the voltage seen at the master’s ILIM input
(VITHM = 0.1 ✕ VLIM(MASTER), see the master con-
troller’s data sheet). Connect a resistive voltage-divider
from the master controller’s internal reference to GND,
with the master’s ILIM input connected to the center tap
(Figure 5). Use 1% tolerance resistors in the divider with
10µA to 20µA DC bias current to prevent significant
errors due to the ILIM pin’s input current:
VILIM(MASTER)
20µA
≤ RB
≤
VILIM(MASTER)
10µA
RA
=
VREF(MASTER)
VILIM(MASTER)
− 1RB
Configure the slave controller so its LIMIT output begins
to roll off after the master current-limit threshold occurs:
VITHS
≥
RCM
VITHM(HIGH)
RDS(ON)(MAX)
+ ∆IINDUCTOR
where VITHS, the slave’s current-limit threshold, is pre-
cisely one-tenth the voltage seen at the slave’s ILIM
input (VITHS = 0.1 ✕ VILIM(SLAVE)). Connect a second
resistive voltage-divider from the master controller’s
internal reference to GND, with the slave’s ILIM input
connected to the center tap (Figure 5). The external
adjustment range of 400mV to 1.5V corresponds to a
current-limit threshold of 40mV to 150mV. Use 1% toler-
ance resistors in the divider with 10µA to 20µA DC bias
current to prevent significant errors due to the ILIM
pin’s input current. Reducing the current-limit threshold
voltage lowers the sense resistor’s power dissipation,
but this also increases the relative measurement error:
VILIM(SLAVE)
20µA
≤ RD
≤
VILIM(SLAVE)
10µA
RC
=
VREF(MASTER)
VILIM(SLAVE)
− 1RD
Now, set the current-limit adjustment ratio (AADJ =
VITHM(HIGH)/VITHM(LOW)) greater than the maximum to
minimum on-resistance ratio (ARDS = RDS(ON)(MAX)/
RDS(ON)(MIN)):
AADJ ≥ AROS
1+
RA //RB
RLIMIT
≥
RDS(ON)(MAX)
RDS(ON)(MIN)
Increasing AADJ improves the master’s current-limit
accuracy but also increases the current limit’s noise
sensitivity. Therefore, RLIMIT may be selected using the
following equation:
( ) RLIMIT
≤
RA //RB RDS(ON)(MIN)
RDS(ON)(MAX) − RDS(ON)(MIN)
Finally, verify that the total load on the master’s refer-
ence does not exceed 50µA:
( )
IBIAS(TOTAL) = RA +
VREF
RB //RLIMIT
+
VREF
RC + RD
≤
50µA
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